DAY 1
OVERVIEW OF IPC CID+ HDI COURSE
0.1 Course Goals
IPC
Students
Instructors
0.2 Day-by-Day Breakdown
Day 1
Day 2
Day 3
0.3 Sample Exam Questions
Multiple choice answers
Based on course material
Based on mathematical equations

SECTION 1: HDI TECHNOLOGY EDUCATION
1.1 Basics of Interconnection Strategies
Single-sided: Advantages/Disadvantages
Double-sided: Advantages/Disadvantages
Multi-layer: Advantages/Disadvantages
HDI: Advantages/Disadvantages
1.2 Density Calculations
Objects to be considered for density calculation
Determining when HDI should/must be considered
Holden predictive analysis formula explained
Hands-on labs
1.3 Vendor Qualification
Fabrication Capabilities
Process Engineers
Score Card for evaluating current/potential fabricator(s)
Quiz
1.4 Materials
Suppliers (Worldwide)
Fabrication Processes
Newer Materials
Hands-on labs

SECTION 2: DESIGN SETUP EDUCATION
2.1 Vias – Ad Nauseum
IPC T-50 Terminology
Advantages/Disadvantages of via interconnection
Other Via Terminology
Quiz
2.2 IPC HDI Type
IPC HDI Type I – What are the characteristics?
IPC HDI Type II – What are the characteristics?
IPC HDI Type III – What are the characteristics?
IPC HDI Type IV – What are the characteristics?
IPC HDI Type V – What are the characteristics?
IPC HDI Type VI– What are the characteristics?
Quiz
2.3 Stackup Methodologies
The Eight HDI Stackup Proposals (Advantages/Disadvantages)
Students
Hands-on labs
2.4 IPC-2152 Current Handling Standard
Why a new standard now?
Power Planes / Split Power Planes /
New Technology: Power Meshes
Hands-on labs
2.5 Electrical Performance
Signal Integrity (SI) Concerns
Power Integrity (PI) Concerns
EMC, not EMI
Balancing these needs into your design
Quiz
4:30 P.M.QUESTIONS AND ANSWERS
5:00 P.M. ADJOURN

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DAY 2
SECTION 3: DESIGN INTERCONNECTION EDUCATION
3.1Generic CAD Tool Setup Strategies
Layers (Signal and Powers)
Vias required
Constraints – Physical
Constraints – Electrical
3.2 Component Placement Strategies
What is DFX/DFM/DFA?
Placement for Internal/External/Combination breakout strategies
Quiz
3.3 General Component Fanout Strategies
External breakout strategies
Internal breakout strategies
When a single fanout within a pad is insufficient
Quiz
3.4 BGA Fanout Strategies
Dog-bone
Extended Via in Pad
Via-in-pad
Hands-on labs
3.5 BGA Escape Routing Strategies
Channels
Boulevards
Optimizing non-power pin areas
Hands-on labs
3.6 Embedded Components
Embedded Resistors
Embedded Capacitors
Optimizing connections to embedded devices
3.7 Routing Strategies
Manual routing versus Autorouting
Routing Strategies: Advantages/Disadvantages
Always Plan for Three Unique Routing Strategies
Hands-on labs

SECTION 4: POST-INTERCONNECTION EDUCATION
4.1 Testing an HDI Design
Planning for testing on your design
Traditional Test Methodologies – Cost Perspective
Advanced Testing Methodologies – Justifying the Expense for Thoroughness
4.2 Documenting an HDI Design
Stackup
Fabrication Notes
Creating Test Criteria Documentation
4.3 Retrofitting/Redesigning Through Hole Designs with HDI
Analyzing Current Opportunities
Prioritizing Your Strategy
When to Evaluate the Re* to see if you are meeting your strategy
Hands-on lab
4.4 Next-Generation HDI Strategies
Currently done elsewhere
Finding industry experts through the Internet
White papers on next-generation ideas
4:30 P.M. QUESTIONS AND ANSWERS
5:00 P.M. ADJOURN

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DAY 3
8:30 A.M. CERTIFICATION TESTING
NOON TESTING RESULTS AND AWARDS