Designing Chips for Real Time Machine Learning
April 1, 2019 | DARPAEstimated reading time: 3 minutes
The current generation of machine learning (ML) systems would not have been possible without significant computing advances made over the past few decades. The development of the graphics-processing unit (GPU) was critical to the advancement of ML as it provided new levels of compute power needed for ML systems to process and train on large data sets. As the field of artificial intelligence looks towards advancing beyond today’s ML capabilities, pushing into the realms of “learning” in real-time, new levels of computing are required. Highly specialized Application-Specific Integrated Circuits (ASICs) show promise in meeting the physical size, weight, and power (SWaP) requirements of advanced ML applications, such as autonomous systems and 5G. However, the high cost of design and implementation has made the development of ML-specific ASICs impractical for all but the highest volume applications.
“A critical challenge in computing is the creation of processors that can proactively interpret and learn from data in real-time, apply previous knowledge to solve unfamiliar problems, and operate with the energy efficiency of the human brain,” said Andreas Olofsson, a program manager in DARPA’s Microsystems Technology Office (MTO). “Competing challenges of low-SWaP, low-latency, and adaptability require the development of novel algorithms and circuits specifically for real-time machine learning. What’s needed is the rapid development of energy efficient hardware and ML architectures that can learn from a continuous stream of new data in real time.”
DARPA’s Real Time Machine Learning (RTML) program seeks to reduce the design costs associated with developing ASICs tailored for emerging ML applications by developing a means of automatically generating novel chip designs based on ML frameworks. The goal of the RTML program is to create a compiler—or software platform—that can ingest ML frameworks like TensorFlow and Pytorch and, based on the objectives of the specific ML algorithms or systems, generate hardware design configurations and standard Verilog code optimized for the specific need. Throughout the lifetime of the program, RTML will explore the compiler’s capabilities across two critical, high-bandwidth application areas: 5G networks and image processing.
“Machine learning experts are proficient in developing algorithms but have little to no knowledge of chip design. Conversely, chip designers are not equipped with the expertise needed to inform the design of ML-specific ASICs. RTML seeks to merge these unique areas of expertise, making the process of designing ultra-specialized ASICs more efficient and cost-effective,” said Olofsson.
Based on the application space’s anticipated agility and efficiency, the RTML compiler provides an ideal platform for prototyping and testing fundamental ML research ideas that require novel chip designs. As such, DARPA plans to collaborate with the National Science Foundation (NSF) on this effort. NSF is pursuing its own Real Time Machine Learning program focused on developing novel ML paradigms and architectures that can support real-time inference and rapid learning. After the first phase of the DARPA RTML program, the agency plans to make its compiler available to NSF researchers to provide a platform for evaluating their proposed ML algorithms and architectures. During the second phase of the program, DARPA researchers will have an opportunity to evaluate the compiler’s performance and capabilities using the results generated by NSF. The overall expectation of the DARPA-NSF partnership is to lay the foundation for next-generation co-design of RTML algorithms and hardware.
“We are excited to work with DARPA to fund research teams to address the emerging challenges for real-time learning, prediction, and automated decision-making,” said Jim Kurose, NSF's head for Computer and Information Science and Engineering. “This collaboration is in alignment with the American AI Initiative and is critically important to maintaining American leadership in technology and innovation. It will contribute to advances for sustainable energy and water systems, healthcare logistics and delivery, and advanced manufacturing.”
RTML is part of the second phase of DARPA’s Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5 billion investment in the future of domestic, U.S. government, and defense electronics systems. As a part of ERI Phase II, DARPA is supporting domestic manufacturing options and enabling the development of differentiated capabilities for diverse needs. RTML is helping to fulfill this mission by creating a means of expeditiously and cost-effectively generating novel chip designs to support emerging ML applications.
Suggested Items
Elementary, Mr. Watson: Ensuring Design Integrity
03/28/2024 | John Watson -- Column: Elementary, Mr. WatsonBack in February, many of us watched the "Big Game." It reminded me of the saying, “It's not how you start that is important, but rather how you finish." It is perfectly okay when you are talking about sports, you get off to a bad first half and need to recover in the second half. However, when it comes to PCB design, this is not a good practice. If things start badly, they usually don't recover. They continue down that same path, costing more money and losing design time.
Arrow Electronics Launches Intelligent Vision Ecosystem
03/27/2024 | BUSINESS WIREArrow Electronics, Inc. is utilizing the onsemi Imager Access System (IAS) module standard for developing intelligent vision solutions for use in robotics, machine vision, commercial cameras and other uses.
Dymax Will Exhibit Light-Cure Solutions for Today’s Electronics at IPC APEX 2024
03/26/2024 | DymaxDymax, a leading manufacturer of rapid and light-curing materials and equipment, will exhibit at the IPC APEX EXPO 2024 in Anaheim, CA, April 9-11.
Synopsys Announces New AI-Driven EDA, IP and Systems Design Solutions At SNUG Silicon Valley
03/25/2024 | PRNewswireSynopsys, Inc. kicked off its annual flagship Synopsys User Group (SNUG) conference in Silicon Valley at the Santa Clara Convention Center with a keynote presentation by Synopsys president and CEO Sassine Ghazi. Ghazi discussed the unprecedented innovation opportunities and challenges that technology R&D teams face in this era of pervasive intelligence.
New North American Product Family Release from Smart Factory Design
03/22/2024 | Smart Factory DesignSmart Factory Design is pleased to announce a new system technology and supply chain model for providing Zero Liquid Discharge (ZLD) Wastewater Recycling Systems to the North American market. Smart Factory Design is an international public benefit company focused on environmental sustainability and autonomous processes for the Printed Circuit Board, IC Substrate, and General Metal Finishing industries.