Cadence’s Brad Griffin Digs Deep Into DDR


Reading time ( words)

KD: Excellent. Let's talk about serial interfaces. Tell us where they’ve come from and where we’re going with them.

BG:  One of the most interesting things in signal integrity is around the serial interfaces and it also sort of mixes with memory interface design as well, which is a parallel bus. With serial interfaces, the way that we typically check compliance on them is by running many signals which we call high-capacity simulation, and by many I mean like millions and tens of millions of bits. We're looking to see how many of those bits actually get transferred correctly. So when you go to the PCI-SIG, the special-interest group, they have a bit-error rate test that they do with hardware. Well we can do the same sort of bit error rate testing with software. Our signal integrity software supports a high-capacity simulation and then lets you look at the eye diagram and just like with PCI-SIG we have that compliance test built into our software.

brad_griffen_cadence.jpgThere are a couple of really interesting things about what's happening in this space. One is the most popular serial interface by far, which is PCI Express. We’ve been at PCIe 3.0 for a few years now, and that’s an 8 Gb/s interface. Most people here at DesignCon are talking about up to 28 or 56 Gb/s, so 8 is a little bit behind the bleeding edge at this point. But what's going to be happening this year is PCI-SIG is going to approve the 4.0 spec, which is moving it to 16. Still maybe not on the bleeding edge, but doubling the data rate is very significant. Here’s one of the cool things we’re showing in our booth: If someone who is using 8 Gb/s today wants to see if their same hardware will support a 16 Gb/s data transfer, we can help them check that feasibility. It’s really quite interesting because you can see by default the answer is probably no, the eye is going to be closed and you’re not going to meet your bit error rate testing. But because these transceivers and receivers have such advanced equalization in them we have what's called algorithmic models that sit on both sides, transmitter and receiver, and this is the same type of stuff we’re going to see in devices that come out and support PCIe 4.0. We can turn on a level of equalization and see if when we boost that signal if we can open up that eye and see if it’s going to meet those compliance requirements that are going to be associated with doubling the date rate from 8 to 16.

That's a pretty interesting thing that's going to be happening in 2015. And when we talked about LPDDR4, that data rate is actually going to go as high as 4266, so that's going to be working in a similar way that serial links were working about two or three years ago. The same equalization that you needed in serial links a few years ago are going to be needed in memory interfaces this year. We will support that with our algorithmic modeling interface. Today we can show AMI modeling associated with DDR4 and LPDDR4 as well as, of course, serial links. It’s just tremendously exciting that, with all this different technology, we get data passed across the ether into the cloud as fast as possible. All this stuff is really exciting, and the fact that we’re able to analyze this and help customers get to market right the first time is what we're really excited about at Cadence, and the Allegro technology is providing that link to getting the product done right the first time. 

KD: Thanks for taking the time to talk with me today, Brad.

BG: Thank you, Kelly.

 

SPONSORED LINKS:

Sigrity™ Portfolio – What’s New

Accurate Power-Aware Simulation for LPDDR4

Enabling Fast and Efficient Product Creation

Cadence® Allegro® Sigrity™ Signal Integrity Integrated High-Speed Design

How a Team-Based Approach to PCB Power Integrity Analysis Yields Better Results

 

RELATED VIDEO: 

 

 

Share

Print


Suggested Items

Roundtable Discussion: App Notes and Fab Notes

11/09/2020 | Andy Shaughnessy, Design007 Magazine
Andy Shaughnessy recently invited four recent contributors—Dana Korf, Jen Kolar, Mark Thompson, and Kelly Dack—to review the June and August 2020 issues of Design007 Magazine, which covered app notes and fab notes, respectively. In this wide-ranging roundtable, the group discusses some of the ongoing challenges related to incomplete and inaccurate design data and why communication can preclude many of these problems. What follows is the transcript from this conversation.

Combatting Thermal Challenges With TRM Software

10/07/2020 | I-Connect007 Editorial Team
Johannes Adam is the creator of a simulation tool called Thermal Risk Management (TRM) used to help PCB designers and design engineers predict hot spots on the board before during layout. He and Douglas Brooks, founder of UltraCAD Design, have used the tool to produce several technical articles and a book on the subject. In this interview, they tackle the biggest misconceptions they see from designers and engineers who deal with thermal management issues.

The Role of EDA Tools in Creating Fab Notes

09/08/2020 | Pat McGoff, Mentor
When discussing fab notes, there’s a lot of focus on what designers should and should not include in the package. But what is the role of EDA tools in this process, and can intelligent data formats streamline the tasks and help eliminate fab notes that are less than fantastic? In this interview, Pat McGoff, market development manager for Mentor, a Siemens Business, speaks frankly about fab notes and what EDA tool companies like Mentor can do to automate this process.



Copyright © 2020 I-Connect007. All rights reserved.