Editor's Note: To read the part 1 of this article, click here.
The second day commenced with a new product launch. “Working together is hard” it read on the screen. Statistics indicated that 33% of new products were late getting to market, of which 28% were late due to insufficient collaboration, and up to 50% of potential revenue could be lost through being late to market. Then the screen read “NEXUS makes it easy!”
Dan Fernsebner introduced Altium’s system-level design-collaboration tool, built to enable schematic, layout, MCAD, and PCB multi-board interactions between team members using a collaboration panel, and to record every action and decision as part of the design history. NEXUS was cloud-enabled and gave members of the design team access to a central database through which they could communicate directly and each view changes and accept or reject them. Whatever changes were made, the design files were immediately updated.
Fernsebner demonstrated the capability of the system with a live exercise. In his example, an end-of-life connector required to be replaced and re-positioned. Four engineers were involved: schematic design engineer, PCB designer, mechanical engineer and system design engineer. Each had the facility to interact with the cloud and push and pull the details relevant to his area of responsibility, whilst observing the consequences on every other engineer’s area. Once the changes had been made, agreed and accepted, everything was automatically updated and recorded and the task had been completed with no ambiguity and no waste of time.
The day’s first industry keynote, “PCBs for Computing Density, From Big Bang to the Automobile,” was delivered by research scientist Andreas Doering from the IBM Research Laboratory, technical design lead for the DOME microserver project, and now piloting the development of the world’s largest radio telescope for exploring the origins of the universe. He explained that DOME was a Dutch government-funded project between IBM and ASTRON in form of a public-private-partnership focusing on the Square Kilometre Array,
Even though the Big Bang was estimated to have taken place 13.8 billion years ago, there was believed to still be some evidence of its occurrence and its consequences, if there was big enough detector and a powerful enough computer to process all the data it collected, which would be more in one day than the whole internet produces in a year—although most of it would be noise. Rather than employing one enormous dish, the Square Kilometre Array would draw on more than one hundred thousand dishes and antennae spread across Africa and Australia to create a collecting area of one square kilometre. Construction was due to begin in 2018.
Based on Doering’s projections on the amount of computing capacity required to process a minimum of 14 exabytes of data per day (where one exabyte equals 1018 bytes), a conventional computer would need several gigawatts of power to drive it. So the demand was for higher computing density, higher performance per watt, and reduced complexity of systems. Enabled by the emergence of powerful embedded-processor cores, a new class of custom-designed “microserver” was in development, with non-enclosed modules comprising system-on-chip, plus DRAM, plus flash, plus power, mounted in multiples on a backplane.
The project required 21 different PCB designs, most of which had been produced on Altium Designer, and he listed the attributes of each. The switch mothercard was a 3.6 mm, 28-layer with back-drilling, six inner impedance-controlled signal layers, with shielding ground layers in-between, and four high-current power supply lanes. At its current state of development, the system consisted of a backplane for 32 compute nodes, of which eight were populated, one switch node, one management node and two storage nodes, with water-cooling. The next stage would be a unit containing two backplanes and a total of 64 compute nodes, representing 1536 cores, 1536 GB of DRAM and 64 SSDs. Besides the primary application in the Square Kilometre Array, Doering saw many potential market opportunities for microservers in scientific computing, internet-of-things, robots and autonomous vehicles.
Back to parallel technical breakout sessions: the choice was between Willem Gruter’s “Verifying your FPGA is correctly connected on a PCB,” Martin Schuster’s “Boost your Altium Design Efficiency with Templates and Shortcuts,” or Jürgen Wolf’s “Embedding Technology—Design and Layout of Printed Circuit Boards with Embedded Components in Altium.” The first two appeared to me to be experts-only advanced tutorials for professional designers. I could identify directly with embedding technology, so I chose Wolf’s session and made sure to grab a seat early because it turned out to be a standing-room-only event.
It was a good choice! Würth Elektronik product manager Jürgen Wolf gave an enlightening insight into three different embedding technologies, ET solder, ET microvia and ET flip-chip and their typical applications, with detailed manufacturing process sequences and design guidelines. He reviewed the benefits of embedding technology in terms of miniaturisation, functionality and reliability, and listed the indicators for choosing a particular technology: ET solder was suitable for active components not available as bare die, and a range of solid SMD components. ET microvia was a highly reliable assembly and packaging technology which could be used for a combination of active and passive components, provided they had copper or nickel-palladium pad metallisation. ET flip-chip was used for fine-pitch components which would otherwise have been wire-bonded. It was not appropriate for passive components.
The process flow for ET solder was to structure the innerlayer core with the SMD component footprint, then to reflow lead-free solder as in typical SMD assembly, then to laminate as a multilayer PCB and finish according to customer requirements.
The process flow ET microvia offered two options: either start with copper foil as substrate and assemble the components face-down with non-conductive adhesive, then laminate as a multilayer and make contact to the components by laser drilling, metallising and copper plating, followed by structuring of the outer layers. Alternatively, assembling the components face-up on the innerlayer core with isotropic conductive adhesive, then laser drilling, metallising, copper plating and outer layer structuring.
The process flow for ET flip-chip began with an innerlayer core structured with the flip-chip footprint, followed by flip-chip assembly using anisotropic conductive adhesive, then multilayer lamination and finishing according to customer requirements.
Wolf gave a comprehensive series of suggestions for project planning, design rules, layout, thickness tolerances and bills of materials for the embedded components, and showed with a live demonstration how Altium Designer could be used for defining the stack-up, the component layer and the component placement and orientation, together with calculation of dimensions and clearances for cavities and workarounds for designing innerlayer solder mask and solder paste images. There were particular rules about grouping of components and safe distances from edges. An in-depth knowledge of prepreg resin flow characteristics was needed to ensure void-free encapsulation.
The final parallel session offered a choice of experts-only specialised tutorials for professional designers: “Adopting Early Analysis of Your Power Delivery Network,” from product manager Andy Haas and field applications engineer Christian Keller; “Conquering Multi-Board Design Challenges to Create Next-Generation Electronics” from global head of technical sales and support Rainer Asfalg and field applications engineer Carsten Kindler; and “Introduction to PCB Design with Altium Designer 18,” with field applications engineer Damien Kirscher. I chose to sit-in on the Rainer Asfalg–Carsten Kindler session, which described the capability of a new feature of the Altium Designer 18 update. Rather than the design of individual PCBs, this went to the next level and considered the management of multi-board systems with particular emphasis on defining and maintaining the connectivity between them, and the mechanical considerations of how they fitted into the enclosure. “A multi-board system only works as well as its worst member!” When questions were invited, the session turned into a very active and informative user-forum discussion.
The closing industry keynote came from Simon Payne, CEO of XJTAG, entitled “Saving Time & Money with JTAG.” He explained that the Joint Test Action Group was originally an electronics industry association initiative for developing a method of verifying designs and testing printed circuit boards after manufacture, and had been subsequently adopted as the IEEE Standard 1149.1-1990 for boundary-scan architecture. JTAG boundary scan technology provided access to many logic signals of a complex integrated circuit, enabling an operating device to be monitored and software and hardware faults to be located. “The good news is it’s already there! You don’t have to pay for it! But are you using it?”
Payne went on to ask, “What is testability?” and commented, “The more testable your design is, the more certain you can be that your test will pick up any defects and your device will work reliably.” He explained the PCOLA-SOQ method for categorising and scoring defects. PCOLA defined the attributes of the component: Presence—is the part there? Correctness—is it the correct part? Orientation—is the part oriented properly? Live—does the part "come alive?" Alignment—is it centred properly on the pad? SOQ defined the attributes of the solder joint: Shorts—are there any shorts? Opens—are there any opens? Quality—is it consistent with the relevant standard?
He discussed the relative strengths, weaknesses and costs of the four test methodologies: JTAG, AOI, X-ray and ICT, in terms of a PCOLA-SOQ analysis. They were appropriate at different stages of the manufacturing process. The benefit of JTAG was that it was available to design engineers. The most important consideration regarding testability was access: a single point of access on a net gave some opportunity for fault detection; multiple points of access gave better detection and the opportunity for fault diagnosis, particularly open circuit location.
Payne reviewed the progress of JTAG over the last decade: costs had fallen and support for non-JTAG devices has become much easier. He stressed that JTAG tools were aimed at board designers as well as production test engineers, and that accelerated in-circuit programming was limited only by flash write speed. Signal integrity in test fixture cabling was becoming an increasingly critical consideration.
He urged designers to think about JTAG as early as possible in the process; the benefits would be realised sooner than might be expected, and time and money could be saved. If JTAG was used to test prototypes, those tests could be re-used on the production line. And accelerated JTAG solutions could be used for in-system programming, both for de-bug and for production.
Lawrence Romine, Altium’s director of Global Business Development, brought proceedings to a close, thanking all who had attended and all who had shared their knowledge and expertise, and the team who had put together such a well-organised and professionally managed event which had exceeded all expectation. The “learn, connect, get inspired” theme was realised with resounding success. Thank you, Altium, for giving me the opportunity to be there.