The Challenge: Eliminate Schematic Design Errors
The schematic is the controlling document for every PCB design. It captures the design intent and drives all downstream processes including simulation, analysis, layout, fabrication, and assembly. As such, it is critical that the schematic accurately reflects the product’s electronic requirements and specifications.
Historically, the all-important task of verifying that the schematic is properly conveying design intent has been a manual process conducted by one or more hardware engineers. This verification is usually performed one sheet or one block at a time, with some automation used to assist in the process such as exporting the bill of materials and/or the netlist to text files or spreadsheets.
Schematic verification is an accepted part of the hardware engineer’s responsibility just as PCB layout verification is an accepted part of the PCB designer’s responsibility. However, with today’s circuit designs becoming more and more complex, time-consuming manual schematic verification is no longer an option. Manual verification of a complex circuit introduces significant risk by not identifying schematic design errors that are, in turn, passed to the downstream processes and ultimately to the fabricated board. This results in costly respins and increased time to market.
In a recent study conducted by the Aberdeen Group, 65% of the companies surveyed cited increasing product complexity as their top PCB design challenge.
The Aberdeen Group’s findings reinforce the criticality of ensuring that the schematic design is error-free throughout the product development process. This article discusses how an efficient, fully automated, schematic review process can be an enabler for design teams to eliminate schematic design errors, thereby reducing costly respins and improving time to market.
To read this entire article, which appeared in the January 2018 issue of Design007 Magazine, click here.