This article briefly introduces the 4-level pulse amplitude modulation (PAM-4) and its application in 400 Gigabit Ethernet (400GbE), to support the booming data traffic volume in conjunction with the deployment of 5G mobile communications. Furthermore, this article also highlights the essential pre-layout effort from signal integrity perspective for physical (PHY) link design on a PCB, including material selection, transmission line design and channel simulation to support 56Gbps data rate that paves the way for seamless communication in 400GbE.
400GbE is a new wired communication standard to accommodate the booming data traffic volume with the implementation of 5G mobile communications. In the implementation of 400GbE communication, electrical interface with 4-level pulse amplitude modulation (PAM-4) signaling over 8 lanes is adopted. The communication of eight lanes at 56Gbps (i.e., 28GBaud) per lane enables the total bandwidth of 400Gbps over the Ethernet. The electrical specifications of 400GbE with PAM-4 signaling are defined in IEEE 802.3bs.
PAM-4 has 4 digital amplitude levels, as shown in Figure 1. It has an advantage over non-return-to-zero (NRZ) signals because each level or symbol in PAM-4 contains two information bits providing twice as much data throughput for the same baud rate. For instance, 28GBaud is equivalent to 56Gbps in PAM-4 and 28Gbps in NRZ respectively.
II. Essential pre-layout effort from signal integrity perspective
According to guidelines, a PAM-4 channel with trace length up to 8 inches on a PCB shall have insertion loss less than 10dB at 14GHz (i.e., Nyquist frequency of 28GBaud) and 20dB at 28GHz (i.e., 2nd harmonic of 28GBaud) respectively to achieve seamless data communication between the transceivers.
To read this entire article, which appeared in the May 2018 issue of Design007 Magazine, click here.