Editor’s Note: Click here to read Part I.
The Microvia Summit on May 16 was a special feature of the 2019 event, since microvia challenges and reliability issues have become of great concern to the PCB manufacturing industry. It provided updates on the work of members of the IPC V-TSL-MVIA Weak Interface Microvia Failures Technology Solutions Subcommittee and opportunities to learn about latest developments in methods to reveal and explain the presence of latent defects, identify causes and cures, and be able to consistently and confidently supply reliable products.
Dr. Michael H. Azarian of CALCE at the University of Maryland explored the effects of design and manufacturing factors on the reliability of microvia interconnects, discussing the relative strengths and weaknesses of blind, buried, isolated, staggered, and stacked microvias in HDI circuits. He stressed this point, “What looks like a relatively simple structure is actually associated with a vast number of design and process parameters that can impact reliability.”
Azarian began by considering quality issues associated with microvia filling by electrolytic copper plating. Incomplete filling or voiding could degrade reliability through localised stress concentration reducing fatigue life. He then showed several examples of corner cracks, barrel cracks, and interface separation, some attributed to inadequate process control, some to brittle fracture of the electroless copper.
Also, Azarian used finite element analysis to help determine the effects of microvia defects and process parameters on microvia lifetime, using fatigue modelling to simulate a series of solder reflow cycles followed by thermal cycling. He commented that the total strain range of the first solder reflow cycle was much larger than that of the second and third cycles due to work hardening of the copper. Fatigue life was affected by the size and shape of voids, and Azarian observed that small spherical voids actually increased the fatigue life, whereas for conical voids, the fatigue life decreased with the void size. Microvia aspect ratio also affected fatigue life when voids were present, and for a given conical void shape and volume ratio, the smaller the aspect ratio, the longer the microvia fatigue life. CALCE developed a second-order regression model to predict the cycles to failure of copper-filled stacked microvias under thermal loading and used finite element modelling for fracture analysis
Then, Azarian highlighted some of the challenges involved in microvia testing and the detection of delamination and cracking, particularly at the early stages of degradation. Advantage had been taken of the high-frequency skin effect to monitor interconnect degradation by observing changes in RF impedance. And time-domain reflectometry at high frequencies provided a further route to the early detection of interconnect failure.
Lance Auer from Conductor Analysis Technologies reported highlights from IPC committee meetings at IPC APEX EXPO 2019 and the movement towards performance-based acceptance testing for microvia reliability. He commented on the shortcomings of testing to existing IPC 6010-series specifications, which often did not identify the failures. There had been many examples of failures after passing all testing requirements, observed at in-circuit test after reflow, at environmental stress screening during box-level assembly, or in the field by the end customer. And traditional microsection techniques were not always capable of detecting many of these defects.
The IPC V-TSL-MVIA Weak Interface Microvia Failures Technology Solutions Subcommittee reported its findings during an open forum at IPC APEX EXPO 2019. In response, IPC issued a warning statement about post-fabrication microvia failures occurring during reflow but remaining undetectable at room temperature.
Several OEMs had been successfully screening lots with D-coupon testing per Method 2.6.27 Appendix A of IPC-TM-650, and IPC was moving away from traditional microsection evaluation towards performance-based acceptance testing. Reflow simulation testing for structural integrity during thermal stress was being added into the IPC-6012E qualification and performance specification for rigid printed boards.
Auer summarised the recommendations for performance-based acceptance testing agreed at the APEX 2019 committee meetings. He demonstrated the thermal profiles for reflow simulation and thermal shock testing and showed examples of change-in-resistance measurements corresponding to microvia failures. The suggested drawing notes described the design of IPC D-coupons, the number to be tested per manufacturing panel, the conditions for reflow simulation and acceptance criteria for change in resistance, the conditions for thermal shock and acceptance criteria for change in resistance, and the reporting of results.
What was the source of the weak microvia interface? According to Jerry Magera and J.R. Strickland from Motorola Solutions, it all began with the microvia target pad. They quoted the example of a field-deployed product failing because of an open circuit in the PCB caused by a stacked microvia fracturing during reflow. Thermal expansion mismatch between copper and laminate induced strain that resulted in a fracture at the interface between target pad and copper via fill. They set out to determine the reason for the weakness at the interface.
Section 188.8.131.52 of the existing IPC 6012E specification gave insufficient information to adequately define the required processes or to control process variation and achieve consistent target pad surface to ensure structural integrity. Magera and Strickland showed a typical laser drill/electroless copper process flow, indicating many stages at which the condition of the target pads could be affected, and listed the process control variables associated with the catalysation and deposition chemistries for electroless copper.
Structural variations in microvia field-failure interfaces on products that had passed existing IPC and OEM validation tests and microsection inspections, but had retroactively failed IPC 2.6.27A testing, had been investigated using microsections produced by focused-ion-beam (FIB) trench-machining techniques. These revealed defects that had been missed by conventional optical microscopy. Three modes of interface failure had been observed: between electroless copper and target pad, between electrolytic copper fill and electroless copper, and within the electroless copper. There was often a mix of all three failure modes.
Scanning electron microscope (SEM) examination of the surfaces of target pads after laser drilling and electroless copper showed some interesting variations in grain structure, which Magera and Strickland explained in terms of the different rates of growth of 1;0;0 and 1;1;1 planes in the face-centred cubic crystal structure of copper. The evidence suggested that substrate morphology, chemistry, and process control all affected the copper deposit structure.
Magera and Strickland recommended further FIB, SEM, and X-ray diffraction studies of microvia target pads (as laser-drilled, before catalyst pre-dip and after electroless copper, correlated against process control data to identify critical control variables) to determine the conditions required to produce consistent interface structures and identify the appropriate copper crystal lattice structure for best practice. And it was proposed that IPC-6012E 184.108.40.206 be updated to better define the requirements for electroless copper.
Speaking with many years’ experience of reliability testing and failure analysis, Kevin Knadle, principal engineer at i3 Electronics, gave a comprehensive presentation entitled “The Keys to 100% Effective Reliability Testing and Failure Analysis of HDI/Microvias.” He commented on the growing concern for microvia reliability, and that reliability field-failures from weak vias cracked in reflow had been identified as far back as 1995, using the current induced thermal cycle (CITC) test. IPC had recently issued a warning statement regarding microvias, and there was currently a move towards performance-based acceptance testing for high-reliability PCBs.
So, what were the critical elements for effective testing of microvias? Knadle advocated the testing of representative stitched coupons to failure, or at least 50 cycles, from room temperature to the product assembly peak reflow temperature, with continuous resistance monitoring and temperature verification. Failure criteria should be based on the measurement of the temperature coefficient of resistance (TCR).
Further, Knadle reiterated the via reflow problem—the reliability threat of vias failing at reflow—but the failures being undetectable by in-circuit tests at room temperature. Therefore, they required testing at reflow temperatures. Knadle listed the attributes of CITC testing: a small single-net coupon, a controlled heat cycle, quick coupon connection, the option to go to 300°C maximum temperature, electrical failure isolation, and temperature coefficient of resistance always measured.
Knadle also explained the CITC cycle and failure criteria, and the via failure mode that was observed as an open or measurable resistance change at or near the peak temperature. The test was 100% effective, and temperature coefficient of resistance was the only way to control coupon temperature with current-induced heating. He gave examples of TCR results and calculations for different microvia and stacked microvia configurations and for different reflow profiles. A process monitor television was used to continuously observe and improve the process.
Testing to failure was quick with CITC, and Knadle believed it made the results “come alive.” He gave examples of the technique in performance-based shipping verification, process and product improvement, and described a method for failure-sectioning that was claimed to be 100% effective. He concluded with recommendations for the 2.6.27A specification update: to include additional reflow temperature options, simplify temperature profile requirement, add TCR measurement for temperature verification, and allow the use of any stitched coupon that represented product vias.
The wealth of knowledge and experience generously shared by the presenters provided an excellent background for a panel discussion on weak-interface stacked microvia reliability, moderated by IPC Hall-of-Famer Denny Fritz as well as Bhanu Sood (safety and mission assurance, NASA Goddard Space Flight Center), Magera, Strickland, Azarian, and Knadle.
In his introduction, Fritz made it clear that there was no intention to scare designers and users away from microvias; they remained a reliable PCB interconnect construction when properly formed and screened by IPC methods. But there was a valuable opportunity to discuss a potential reliability issue primarily associated with multiple levels of stacked microvias. Fritz stressed that staggered or even single-level microvias still needed to be manufactured carefully and tested to IPC standards. The other objectives of the Microvia Summit were to discuss the best industry efforts to date to mitigate weak-interface microvias through recently adopted design parameters, test protocols, and product sorting, and to solicit attendee support for the various sub-teams of the IPC Weak Microvias Task Group.
Additionally, Fritz included a review of the background and history of the problem as described in the IPC-WP-023 white paper, and an introduction of the panel members and their interest in this problem, followed by an open discussion. A big fishbone diagram illustrated the complexity of the subject, and the project categories were defined and the working teams nominated.
The obvious long-term objective was to provide design, material selection, and processing guidance to enable the industry to achieve reliable higher density structures. Fritz implored delegates to support the work of the IPC V-TSL-MVIA Weak Interface Microvia Failures Technology Solutions Subcommittee, contribute relevant data with the assurance that sources would not be disclosed, and join one of the working teams investigating this perplexing and currently expensive PCB industry problem.