This article discusses the impact of interconnection inductance on the impedance of the decoupling capacitor, which influences the power integrity of the PCB. The investigation is performed with 3DEM simulation by varying the trace length and height of stitching vias that connect the decoupling capacitor across the power rail and ground.
On a PCB, a power distribution network (PDN) with low impedance across the wideband is required to transfer power with low switching noise and high stability from the supply to the digital and analog ICs. Each decoupling capacitor—together with its interconnection inductance—are the major factors that contribute to the impedance of the PDN on a PCB. As shown in the cross-sectional view of the PCB depicted in Figure 1, interconnection inductance is formed by the traces and stitching vias hooking up the decoupling capacitor across the power rail and ground (e.g., Loop 1, Loop 2, and Loop 3). This parasitic inductance is directly proportional to the stitching via height and trace length, as governed by Equations 1 and 2, respectively.
Furthermore, referring to the directly proportional relationship between impedance and interconnection inductance in Equations 3 and 4, it is crucial to keep the interconnection inductance low to minimize the impedance of the PDN, which is achievable by reducing trace length and stitching via height.
To read this entire article, which appeared in the July 2019 issue of Design007 Magazine, click here.