Flexible Thinking: IC Package Footprints—Why So Many and How Many Is Enough?

The integrated circuit is credited to both Jack Kilby and Robert Noyce. Kilby was an experimentalist who had worked at CentraLab in Milwaukee, and a purveyor of ceramic insulators with printed conductors (true printed circuits, if you will). He was evidently inspired by his work in ceramic printed circuits and saw how the technology could be used to integrate discrete transistors to make a functional circuit block; thus, he was the first to reduce the concept and demonstrate it in his first few months at his new employer, Texas Instruments. Noyce had a similar vision at Fairchild Semiconductor, a company he co-founded, but he used a more thought-out engineering approach to develop ICs.

The challenge for both approaches upon completion of the IC was how to protect it and make it more useful; thus, the IC package was born. TI was again first out of the gate, delivering ICs in ceramic packages with flat peripheral leads on two sides. These were used on NASA’s Apollo computers and the ICs were surface mounted. Fairchild had a different and less expensive idea—the dual in-line package (DIP) with the die attached and interconnected to a lead frame, then protected with an epoxy. Its leads were formed in a manner that allowed them to be soldered into through-holes of a PCB. 

The DIP package became the preferred format and dominated for most of the early years. It is still in use today, though it would likely be much cheaper to use a more modern format of the era and integrate advancements to bonding such as tab bonding, double bonding, and varying wire diameter.

However, from a performance perspective, skew, clock speed and frequency requirements soon exceeded the limitations of signal through wire, through DIP pin, down to the plated holes and through the PCB, to keep up with electronic performance demands. In the 1980s, surface mount technology was identified as the best way to achieve what had become the prime objectives of electronic product developers (i.e., faster, smaller, cheaper, lighter, and better). Surface mount technology offered all these benefits. However, little attention was given to basic geometry and the arithmetic relationships between the package dimensions and the trace and via routing implicit in the deployment of these newer package types into a PCBA.

To plan for the future, a planning convention was required. This resulted in the arguably arbitrary “80% rule” of generational package lead pitch reduction. By its very definition, the “rule” combined both legacy Imperial measurements and metric measurements. The resulting conversion issues triggered an explosion in package types: pin grid arrays (PGA), small outline packages (SOP), thin small outline packages (TSOP), quad flat packages (QFP), land grid arrays (LGA), and ball grid arrays, to name but a few. These packages had many different lead shapes: flat, straight, gull wing, J-lead, and truncated, among others.

Thus the 80% rule also resulted in an explosion in lead pitches, which assured the end of easily designed routing layers with multiple lead pitches employed in a common design. For the reader’s consideration, ponder this: During the era dominated by through-hole devices there was fundamentally one lead pitch of 0.1” or 100 mils. If one has ever visited an electronic hobbyist’s store, one may have noticed what appeared to be blank epoxy boards with hundreds of holes drilled in them in a gridded fashion. They are commonly referred to as “bread boards” and they allow hobbyists to more easily assemble their circuit designs using through-hole components such as DIPs, TO cans, and axial leaded discrete devices. 

The causes for the explosion were pretty much two-fold. First, the global electronic community, including the U.S., agreed to use the metric system for all measurements related to electronic production. This included outlines and lead pitches. The second was an agreement to follow the 80% rule, which held that every subsequent generation of lead pitches should be 80% of the previous lead pitch (or as close as practical). Thus, legacy pitches such as 100 mil became 2.54 mm, and 50 mil became 1.27 mm. Other finer pitches beginning with 1.25 mm were 1.0 mm. 0.8 mm, 0.65 mm, 0.5 mm, 0.4 mm, 0.3 mm, 0.25 mm, and 0.2 mm. The result is that today, there is a mind-numbing number of package options.

Earlier generation designers demanded that planning and math come first. In the tape and rubylith era (horse and buggy days, I know), math ruled. The completed schematic was bedrock, and finally the BOM served to provide quick reference. When CAD became stable and made it easier to integrate the “hard math” of the EE to a reasonable degree, the math began getting kicked to the curb. Today, fewer and fewer designers have the “scar tissue” of the earlier veterans and thus have the ability to fully appreciate the fundamental importance of planning.  

The 80% rule was not optimum but satisfactory for the early SMT industry. Where it missed opportunity was when it was applied to area array packages such as BGAs and CSPs. Area array land patterns have an intrinsic advantage: If all devices conform to the use of a common base grid such as 0.5 mm or 0.1 mm, trace, via, and plane artwork creation is streamlined because the component count options drop dramatically and layer counts can be significantly reduced. The lesson is this: When lead pitches are fewer in number, vias fall on larger grids, and the routing lanes (trace + gap) align, thus creating less “hypotenuse diagonal” trace length across the circuit layout.

This is graphically illustrated in a design comparison done by PCB design master Darren Smith of Athena Tech and published in Solderless Assembly For Electronics: The SAFE Approach, available for free download in the I-Connect007 eBook library.

The sage CEO of a consulting company I worked for in the late 1990s was often heard to say, “Too soon old, too late smart,” when seeing that simple solutions were often overlooked or unrecognized in our problem-solving efforts. However, I have attached to that thought another time-worn aphorism: “Better late than never.” We are learning beings if we allow ourselves permission to do so and think beyond the pale. As Mark Twain said, “It's not what you don't know that gets you into trouble; it's what you know for sure that just ain't so.”

So, I believe the fundamental answer to the question posed in the title of this column is that there are far too many options. JEDEC allows virtually any package outline and pitch configuration to be registered and we are overloaded with options. I personally believe that fewer options, especially when all components share a common lead pitch for IC package terminations (my suggestion is 0.5 mm, the pitch below which soldering becomes progressively more difficult) is both simpler and better for design and manufacturing. However, one of the strange ironies of achieving simplicity is that it generally takes more forethought and discipline to execute a simple design than it does for more complex ones. So it goes.   

Note: Thanks are extended to design expert Darren Smith for his reviewing skills and valuable comments. 

This column originally appeared in the February 2021 issue of Design007 Magazine.



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