Happy’s Tech Talk #10: Optical Alignment/Coupon Welding for Stackups

In this month’s column, I will discuss optical alignment for pinless lamination stackup, a topic that complements the induction lamination in my November 2021 column.  Examples of this type of equipment are seen in Figure 1.

Pin tooling plates have been used for lamination since it first started sometime in the 1960s. I first encountered multilayer stackup when I was assigned to increase capacity for our multilayer output in 1972. This was to accommodate the growth of our computer business. Unfortunately, the explosive growth of our calculator orders in 1973 required that we look for numerous vendors to produce the six-layer logic board in the HP-35 calculator.

Hewlett-Packard evolved from using four small holes in our pin lamination to using a four-slot center-line pin with post-etch punch in 1974. Registration experiments on this transition were highlighted by a DOE in Chapter 3, Figure 4 of my book, 24 Essential Skills for Engineers1.

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Pin Lamination

Although many schemes have been used, the most popular is the four-pin center-line slot approach. Here a high-precision tooling template with mechanical pins is used for the lay-up and registration. The inner layers must first be prepared with the corresponding registration holes. These holes are generally drilled or punched post etch. The prepreg must also have holes for the pins. These holes do not have to be precise, and they can be 1 or 2 Happy_July_Fig2_cap.jpgmm larger than those of the inner layers. Stainless steel shims and release film are employed between groups of stackups (called books). For the conventional vacuum-heated hydraulic multilayer press, numerous tolerances lead to misregistration of the various inner layers. Figure 2 illustrates six such tolerances from an excellent paper by Anthony Faraci.2

Pinless Stacking
Around 1999, Faraci, who had been working with multilayer tooling for nearly 15 years, started working on optical alignment. He needed a method to hold layers together, so he looked at eyelets (rivets), hot heads, ultrasonic, and induction. After months of development, he settled on induction and came up with a scheme to “weld” the many inner layers together rather than use the common rivets or plate pins. This has evolved to where welds can be located to interior spots on the I/L core. The pinless systems, with innerlayer welding are also available for traditional pin layup.

Process of Operation
The process of using optical alignment is similar to manual layup, only more accurate and faster, with checks to ensure material order and orientation. The process is shown below:

  1. Place the lower lamination plate in position on the layup table and begin layup as usual up to the first separator plate.
  2. After placing the first separator plate in location, place the untooled copper foil (this foil will be outside layer n).
  3. Next place the untooled prepreg (this is all the prepreg between layers n-2 and n-1).
  4. Place the prepreg along the two perpendicular laser layup lines (Figure 3).
  5. Continue placing material up to layer (core) 1 and 2 then activate the welding head.
  6. Place the welded package along the two perpendicular laser lines. The welded package consists of layers 2 to n-1 with all the associated prepreg welded in place between all the layers.
  7. Place the untooled prepreg (this is all the prepreg between layers 1 and 2).
  8. Place the untooled copper foil (this foil will be layer 1).
  9. Place the next separator plate and repeat the process for the entire book.

The inner layers must first be prepared with the corresponding fiducial targets on top and bottom side for the optical alignment (Figure 3). The prepreg has no need for any hole/punch. The inner layers must have weld coupons etched in the reserve zones on both top and bottom sides (Figure 3), and can be placed anywhere along the edges of the lamination plate or inside the image area.

The use of fiducial targets etched in the layers to align through image processing via CCD cameras is the critical alignment step. This process results in lower manufacturing and maintenance cost due to the elimination of the pins, bushings, and tooled separator plates on the lamination process.

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In today’s best fit on pin lamination technology guarantees around 75 µm for layer-to-layer registration, while optical registration measures each layer to get the front to back image registration as well the geometry shape of each core and can align inner layers with a tolerance of ±15 µm (using direct digital imaging). This is possible because each core is individually inspected and can be rejected as quality control according to a tolerance specification. This new generation of the induction bonders provides a capability to place multiple numbers of bonding points in any location of the multilayer stack for best registration.

Those bonding spots work as virtual pins to help the scale constrain, similar to multiple tooling pins around a single PCB. The bonding points can be placed anywhere in the CAD design, the machine is capable to read and decode the CAD file jobs, and automatically know the coordinates for each bonding location of the panel.

Four bonding heads with independent movement in X and Y axes allow the movement of each head to any location and provide fast speed for complex panels that require many bonding locations for best registration and multilayer handling. With cores being as thin as 25-50 µm, and sub-laminations common, the welding process can accommodate these variations as well as coppers from one-third to three ounces. Optionally, the registered and bonded multilayer panel could be automatically unloaded at a rear unloading station that could be equipped with a trolley. Also, one plastic protection sheet can be automatically inserted between each panel. The welded coupon bonding process is seen in Figure 4. The welded book can withstand the dilations and shrinkage of the hot press cycles, thereby providing the best possible linear movement of all layers in a multilayer stackup, reducing the internal stress that causes warping and deformations, and moreover reducing the distortions and misalignments between inner layers.

The welded stackup multilayer can be X-rayed to check before and after lamination for compensation adjustments.

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Technical Requirements
The key component to this imaginative process is the induction welding heads. Figure 5 shows three different designs for such induction heating systems. The ability to change the energy and pressure on the coupons is Happy_July_Fig5_cap.jpgimportant as materials and constructions change. As multilayers of rigid, flex, and rigid-flex change and become more complex, these welding heads also will probably change.

Weld Coupons
The weld coupons on the perimeter of the inner layer cores replace the old punched or drilled holes. The coupons are varied, but in the range of six to 10 mm wide by 15 to 40 mm long copper and recommended copper clearance. All have solid copper decals as seen in Figure 6.

Each equipment supplier has much more detail available from the many years they have been supplying systems.

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Conclusion
As Figure 7 illustrates (a complex 32-layer multilayer), the optical alignment process with the welding of all the cores together improves the registration in multilayer lamination. Coupled with the time savings for layup and the cleanup of epoxy around pin plates, pinless lamination can be a great productivity and quality improvement. This is shown by the more than 250 systems being sold since 2000. The optical and pin alignment systems with their induction core welding have also been adapted for flex and rigid-flex layups. The advantages of pinless:

  • Increased layer-to-layer registration accuracy
  • Increased process predictability and registration data
  • Ability to characterize lamination press process
  • Ability to register thin cores accurately and consistently
  •  Flexibility utilizing lamination plates
  • Plates do not need tooling holes; this allows the plates to be used for multiple panel sizes, and thus fewer sets of lamination plates are needed
  • Separator plates also do not need tooling holes; this allows the plates to be used for multiple panel sizes, thus fewer sets of separator plates are needed
  • Cleaner operation; cleaning plates are easier to clean; there are no resin filled tooling holes
  • Copper foil does not need clearances for tooling pins, as foil is easily damaged when trying to lay up on pins
  • Prepreg does not need clearances for tooling pins which minimizes prepreg dust
  • There will be more flexibility in panel sizes without the restrictions of the pins
  • The lamination pins and bushings are eliminated, thus eliminating a consumable
  • Depinning is not necessary

References

  1. 24 Essential Skills for Engineers, by Happy Holden.
  2. “Optical layer-to-layer Alignment,” by Anthony Faraci, The PCB Magazine, June 2012, pp.40-47.

This column originally appeared in the July 2022 issue of PCB007 Magazine.

Back

2022

Happy’s Tech Talk #10: Optical Alignment/Coupon Welding for Stackups

08-02-2022

In this month’s column, I will discuss optical alignment for pinless lamination stackup, a topic that complements the induction lamination in my November 2021 column. Pin tooling plates have been used for lamination since it first started sometime in the 1960s. I first encountered multilayer stackup when I was assigned to increase capacity for our multilayer output in 1972. This was to accommodate the growth of our computer business. Unfortunately, the explosive growth of our calculator orders in 1973 required that we look for numerous vendors to produce the six-layer logic board in the HP-35 calculator.

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Happy’s Tech Talk #9: Radars, Missiles, and the World’s Costliest Computer

07-19-2022

Let’s have a little fun and walk back nearly 70 years into the history of electronics and computers. What was the world’s costliest computer and why? The answer is not today’s supercomputers, nor computers built during World War II. Instead, it lies in a real-time air defense radar system built during the height of the Cold War of the 1950s that had left the U.S. extremely vulnerable to a Soviet bomber attack. This was the beginning of a North American strategic defense system, eventually known as the Semi-Automatic Ground Environment System (SAGE).

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Happy's Tech Talk #8: Copper Etchant Regeneration

05-31-2022

Copper has become a valuable metal, and with the growth of EV has come higher currents needed in PCB with increasing weight of copper in PCBs. This creates the need for increased copper etching and consumption of copper etchants. Today, in an effort to recoup some of that cost, increasingly more extraction and recovery units are being installed in PCB facilities around the world. Annual profit generation from recovering copper and regenerating PCB etchants has the potential to reach six figures.

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Happy's Tech Talk #7: Next Generation Application Specific Modules

05-02-2022

In 1965, Gordon Moore predicted that the number of transistors that could be packaged into a square inch of space would double every year for the near future. Although his projection was later revised to every 18 months, Moore’s Law has withstood the test of time for five decades. Today, we are beginning to see obstacles to this type of exponential growth due to the inherent limits associated with silicon lithography, packaging of the devices, and component placement on PCBs.

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Happy's Tech Talk #6: Looking at the Process of Repanelization

03-28-2022

I have spent many years in printed circuit fabrication, including nearly 20% of my career in Asia. One problem that concerns all fabricators is the issue of “How many ‘X-outs’ are allowed per assembly sub-panel array? Here are a couple of solutions I have used and encountered in my travels.

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Happy's Tech Talk #5: Advanced Boards for Heterogeneous Integration

03-07-2022

The expansion of IC functionality usually progresses with the shrinking of IC geometries, called “Moore's Law” after Gordon Moore who first coined the phrase. But now that geometries are below 5 nm, the costs and difficulties are creating a barrier to much further advances. So, the solution seems to be to mix IC die on the same substrate as a system-in-package (SiP) that is now called heterogeneous integration (HI).

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Happy's Tech Talk #4: Semi-Additive Processes and Heterogeneous Integration

01-31-2022

The semi-additive processes (SAP) are not new. I first used them with a novel process back in 1978. MacDermid had a novel SAP process called PLADD II (PLAted Additive). It was an anodized aluminum foil applied to laminates that we could easily etch off after drilling and continue with a special electroless copper for thin metallization.

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2021

Happy's Tech Talk #3: Photonic Soldering

12-20-2021

Printed Electronics (PE) continues to be a growing technology. But one of the advantages, as well as a drawback is using low-cost substrates, like paper, that cannot take the temperature of solder paste reflow. Also, the inks need to be cured. One current way to cure the printed inks is with ultraviolet radiation curing, such as used with solder mask or legend inks.

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Happy's Tech Talk #2: Induction Lamination

11-23-2021

Multilayers have been around about as long as the printed circuit. The industry has always used heated hydraulic lamination presses to produce these multilayers, with the introduction of vacuum assist in the 1980s. But recently, with the encouragement of GreenSource Fabrication, induction lamination has been perfected by Chemplate Materials of Spain. Chemplate had introduced the use of induction-pinning by optical alignment of innerlayers for multilayer stackup in the early 2000s. This was to go with another innovative way to laminate innerlayers together—the Italian CEDAL resistance-foil vacuum-press, which had some early adopters.

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Happy’s Tech Talk #1: Vertical Conductive Structures (VeCS)

10-22-2021

The industry has not had many new structures in the last 60 years. Multilayers have continued to evolve with thinner materials, smaller traces / spaces as well as drilled vias. It’s been nearly 40 years since Hewlett-Packard put their first laser-drilled microvia boards into production for their innovative Finstrate process.

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2017

Happy’s Essential Skills: Tip of the Month—The NIST/SEMATECH e-Handbook of Statistical Methods

07-05-2017

In the 1990s, the National Bureau of Standards was distributing a popular statistical document, the Handbook 91, written by Mary Natrella of the NBS Statistical Engineering Laboratory. A request by Patrick Spagon of the Statistical Methods Group of SEMATECH to update the NBS Handbook 91, Experimental Statistics, led to the creation of a project team from NIST and SEMATECH to create a new web-based statistical handbook including statistical software.

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2016

Happy's Essential Skills: Understanding Predictive Engineering

12-16-2016

New product realization and design for manufacturing and assembly (DFM/A) have now started to become more visible as programs that can improve a company’s time-to-market and lower product costs. Many programs are underway by many companies and what is now needed is a framework to coordinate the application of these programs. This column will cover the interactions of DFM/A and the need for development of a new framework to coordinate the trade-offs.

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Happy’s Essential Skills: Technology Awareness and Change

11-22-2016

From Happy Holden: A long-time printed circuit-industry friend of mine, Martin Tarr, an instructor at University of Bolton, UK, is a leading expert on change. He wrote an excellent tutorial for his university course on electronics manufacturing. With permission from Tarr, I am including a portion of it here as the basis of this column, starting after the graph in Figure 2. But first, a few thoughts of my own.

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Happy's Essential Skills: 10-Step Business Plan Process

11-03-2016

It takes more than just a good idea to exploit that brainstorm of yours. Hewlett Packard’s “10-Step Business Plan Process” is the format to present an idea or product in a fashion that will answer most questions that management may have about a product or idea.

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Happy's Essential Skills: Lean Manufacturing

10-19-2016

Lean doesn’t have to exist in manufacturing alone. Lean is a fairly recent principle that can apply to all of our goods and services. For those of you not familiar with Lean, I recommend the free E-book "Survival Is Not Mandatory: 10 Things Every CEO Should Know about Lean" by Steve Williams, a regular columnist for I-Connect007.

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Happy's Essential Skills: Metrics and Dimensional Analysis

10-05-2016

After 20 of my columns, readers probably realize that I am an analytical person. Thus, I dedicate this column to metrics—the method of measuring something. I mentioned the four levels of metrics in my June column "Producibility and Other Figures of Merit." I also introduced the five stages of metrics in the second part of the column "Design for Manufacturing and Assembly, Part 2." This column completes the discussion with a look at dimensionless quantities.

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Happy’s Essential Skills: Recruiting and Interviewing

09-29-2016

Hopefully, your career has progressed to the point that you are empowered to recruit your own team or a key person for your team. There are always technical people looking for better jobs, but many times, the most talented are busy doing their work and not looking for a new opportunity.

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Happy’s Essential Skills: Computer-Aided Manufacturing, Part 2 - Automation Examples

09-22-2016

Semiconductor fabs like to avoid writing custom software to fit all of the idiosyncrasies of individual processing systems. So HP developed PC-10 to handle IC process equipment by separating it into general classes. SECS II was a mandatory prerequisite of the equipment before an interface to PC-10 could be developed.

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Producibility and Other Figures of Merit

06-10-2016

Metrics are data and statistically backed measures. It is always expedient to base decisions on data and metrics, for example, in PCB design. These measures can be density, first-pass yield connectivity or in this context, producibility. These measures are the basis for predicting and planning a printed circuit design. But what if a metric doesn’t exist? Then you can create the next best measure, the Figure of Merit

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Learning Theory/Learning Curves

06-01-2016

Learning is not instantaneous! Nor is progress made in a steady manner, but at a rate that is typified by one of two basic patterns. In some cases, plateaus will be seen in learning curves. These are caused by factors such as fatigue, poor motivation, loss of interest, or needing time to absorb all the material before progressing to new. This column will not go into details of how learning is achieved, but will summarize some of these theories.

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Happy’s Essential Skills: Project/Product Life Cycle

05-18-2016

The product, and or project (process) life cycle (PLC) is fundamental to a corporation intent on developing new products or processes. It sometimes is called the new product introduction (NPI) process but that is only half of the life cycle. There is product support, enhancement and eventually, obsolescence.

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