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November 15, 2026 
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Koh Young’s Answer to Wafer-level Inspection Challenges

Marcy LaRont, I-Connect007

At SEMICON West, I caught up with Allen Phung, head of sales at Koh Young America, where we pivoted from our more traditional focus on SMT-related tech to talking about semiconductors and advanced packaging. Koh Young’s semiconductor business provides inspection and metrology systems for advanced packaging, including micro-solder deposits, high-density substrates, and wafer-level packaging, addressing the demanding requirements as components shrink and interconnect complexity grows.


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Nordson: Protecting Yield as Packaging Complexity Grows

Marcy LaRont, I-Connect007

As AI and high-performance computing push advanced packaging toward greater complexity, manufacturers must expand capacity while protecting yield on increasingly valuable assemblies. At SEMICON West, Nordson Electronic Solutions’ Jeanine Norlin, senior manager of marketing, and Liam Thorp, product line manager, discuss how the company is addressing those demands through plasma surface treatment and precision dispensing. They explain how plasma improves wettability and underfill flow, how the ASYMTEK Vantage XL handles large-panel warpage, and why coordinated process expertise across Nordson’s businesses is becoming more important for manufacturing reliability.


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Scale-out: From Individual Servers To Interconnected Compute Systems

Chetan Arvind Patil, Marvell Technology

The semiconductor industry is moving beyond traditional chip-level scaling toward interconnected computing architectures. Growing demand for AI, high-performance computing (HPC), and data-intensive applications requires greater computing capacity, memory bandwidth, and communication efficiency. As we know, advanced packaging plays an important role in supporting the semiconductor technologies that enable these systems. While scale-up increases the capability of tightly coupled computing systems, scale-out enables those resources to work together at a larger infrastructure level.


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Below the Surface: What Actually Works When Designing Electronics for Harsh Environments

Chandra Gupta, Remtec Inc.

Ask engineers how to design electronics for extreme environments, and you’ll hear plenty of confident answers, like “Use thicker copper” or “Add a heat sink.” That advice is useful, but it is not enough. When electronics fail in harsh environments because of temperature, shock, and vibration, it is rarely due to a single obvious mistake. More often, failure results from a chain of small, “good enough” decisions that cannot withstand extreme stress.


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Events

Dates Event Name Location
Nov 29 - Dec 4, 2026 2026 MRS Fall Meeting & Exhibit — Symposium EL06: Advancing High-Performance Chiplet Architectures Through Materials Innovation and Integrated Design Boston, MA
Dec 1 - 4, 2026 2026 IEEE 28th Electronics Packaging Technology Conference (EPTC) Singapore
Dec 4 - 6, 2026 Advanced Semiconductor Packaging Yield & Reliability Workshop Bengluru, India
Dec 6 - 9, 2026 IEEE-IDSPS 2026 Global Semiconductors to Systems, Research & Technology Conference Visakhapatnam, India
Dec 7 - 8, 2026 ISSM 2026—International Symposium on Semiconductor Manufacturing Tokyo, Japan
Dec 9 - 11, 2026 Advanced Packaging and Chiplet Summit (APCS) 2026 Tokyo, Japan
Dec 14 - 16, 2026 19th IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS 2026) Chandigarh, India
Dec 15, 2026 BGA and BTC Hidden-Joint Inspection, Acceptance and Reliability Requirements Malaysia
Dec 18 - 20, 2026 14th International Conference on Intelligent Systems and Embedded Design (ISED-2026) Hanamkonda, Telangana, India + Online
 
 
 
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