Advanced packaging is driving feature sizes below 50 microns, forcing IC substrates and UHDI PCBs into overlapping territory. Following his presentation at the Pan-European Design Conference (PEDC) in January, Jan Pedersen, director of technology at NCAB Group, spoke with us about how heterogeneous integration, evolving HDI roadmaps, and supply chain pressures are shaping the next phase of advanced packaging.

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The rapid rise of artificial intelligence has fundamentally reshaped the demands placed on semiconductor technology, and nowhere is it more evident than in advanced electronic packaging. A recent episode of the Global Electronics Association’s Executive Pulse webinar series, featuring Dr. Hemanth Dhavaleswarapu of AMD as the first of two esteemed presenters, provided a comprehensive overview of chip-level packaging. He outlined the evolution of AI workloads in forcing a rethinking of everything from chip architecture to data center design, with packaging now playing a central role in enabling continued performance scaling.

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In my last column, I described the ceramic substrate itself, and why material choice matters so deeply in RF, microwave, and millimeter-wave applications. Dielectric constant, loss tangent, thermal conductivity, stability across temperature, and frequency are the physical rules that govern whether a signal arrives intact or collapses into noise.

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