Stitching Capacitor: Crosstalk Mitigation for Return Path Discontinuity

Estimated reading time: 2 minutes

This article discusses the impact of stitching capacitors in mitigating signal crosstalk due to return path discontinuity during layer transition on PCB. The investigation was performed with 3DEM simulation using Keysight EMPro.  

Introduction

In electronic systems, signal transmission exists in a close loop form. The forward current propagates from transmitter to receiver through the signal trace. On the contrary, the return current travels backward from receiver to transmitter through the power or ground plane right underneath the signal trace that serves as the reference or return path. The path of the forward current and return current forms a loop inductance. It is important to route the high-speed signal on a continuous reference plane so that the return current can propagate on the desired path, directly beneath the signal trace.

When the return path is broken due to the switching of reference planes with different potential, e.g., from ground to power or vice versa after layer transition on PCB, the return current might detour and propagate on a longer path, which causes a rise in loop inductance. This might lead to the sharing of a common return path by different signals that pose a high risk of interference among the signals due to higher mutual inductance. This interference results in signal crosstalk. To mitigate the crosstalk due to return path discontinuity (RPD), stitching capacitors are mounted on the PCB to serve as a bridge between the two reference planes of interest on different PCB layers.

Analysis of Signal Crosstalk

To investigate the impact of stitching capacitor in mitigating signal crosstalk due to RPD during layer transition on PCB, three simulation models of 3DEM are constructed. In model 1A (Figure 1), two signal traces with 50 ohm characteristic impedance in single-ended mode on the top PCB layer transition to the bottom layer using vias. Each segment of the signal traces on top and bottom layers is 100 mil long and 5 mil wide. Meanwhile, the diameters of the via barrel and pad are 5 mil and 7 mil respectively. The PCB stackup shown in Figure 2 is applied to this 3D model, where solid planes exist on layer 2 and 3. All the four copper layers are 1.2 mil thick and FR-4 material is used as the PCB substrate.

The two signal traces are 15 mil apart, which is triple the signal trace width for minimum crosstalk due to forward current propagation. A stitching via is placed 20 mil off each signal via, connected to the reference plane on layer 2 and extending to layer 4. However, voids are placed on the layer 3 reference plane to break the electrical connectivity between the planes on layer 2 and 3. This simulates the effect of RPD on signal crosstalk by switching the reference from ground to power or vice versa after the signal layer transition through the via.

To read this entire article, which appeared in the June 2019 issue of Design007 Magazine, click here.