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Current IssueShowing Some Constraint
A strong design constraint strategy carefully balances a wide range of electrical and manufacturing trade-offs. This month, we explore the key requirements, common challenges, and best practices behind building an effective constraint strategy.
All About That Route
Most designers favor manual routing, but today's interactive autorouters may be changing designers' minds by allowing users more direct control. In this issue, our expert contributors discuss a variety of manual and autorouting strategies.
Creating the Ideal Data Package
Why is it so difficult to create the ideal data package? Many of these simple errors can be alleviated by paying attention to detail—and knowing what issues to look out for. So, this month, our experts weigh in on the best practices for creating the ideal design data package for your design.
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Sign Up For Mentor’s July 21 Webinar: FPGA-PCB Co-design
July 9, 2020 | Mentor, a Siemens businessEstimated reading time: 1 minute
Today’s leading-edge systems require a modern FPGA I/O optimization interface that enables you to quickly perform pin swapping and layout-based I/O optimization within the PCB design flow. Fact is, the lack of, or poor FPGA I/O optimization often leads to longer routing cycles and longer trace lengths which in turn result in the need for additional signal layers and vias which can impact signal integrity. A design tool flow with FPGA I/O Optimizer technology eliminates the barriers between FPGA and PCB designers and provides “correct-by-construction” FPGA I/O assignment allowing pin swapping and layout-based I/O optimization within the PCB process.
The ability to read in, export and synchronize FPGA designers’ HDL and constraint files ensures full consistency during the iterative concurrent design process. Incidentally, it also allows creating high pin count FPGA PCB parts ready for instantiation in minutes. Modern FPGA I/O optimization helps you not only accelerate design time-to-market, but also reduces manufacturing costs.
In this webinar by Mentor, a Siemens business, attendees will learn how modern FPGA I/O optimization can help you not only accelerate design time-to-market, but also reduce manufacturing costs.
What Attendees Will Learn
- How to create a multi-thousand pin FPGA part in minutes
- How to enable collaboration between FPGA and PCB designers
- How to optimize FPGA pin assignment in the context of the PCB layout
Who Should Attend
- Electrical engineers
- PCB designers
- Engineering managers
- Anyone interested in FPGA-PCB co-design
Date/Time
July 21, 2020
2-3 PM London Time
July 21, 2020
2-3 PM Eastern Time (US)
To register for this webinar or for more information, click here.
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