Designers Notebook: Panel-level Semiconductor Package Design Challenges


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Semiconductor package specialists continually work to improve high-volume manufacturing process efficiencies while reducing manufacturing costs. A majority of the commercial semiconductors are built-up on the surface of a circular-shaped silicon wafer with metalized terminal features at their perimeter to accommodate wire-bond interface with a lead-frame or package substrate. To enable direct, face-down mounting to a package substrate or host PCB, the aluminum wire-bond sites on these products must first be processed to provide an alloy (typically copper) that will accept traditional solder ball or bump termination features.

When die have a perimeter terminal spacing that is considered too close for efficient circuit routing, it is common practice to employ an additive metalization process on the active surface of the die to provide a conductive interface from the wire-bond lands at the die elements perimeter to a wider-spaced and more uniform array configured terminal pattern.

Solberg_fig1_0520.jpgCommonly referred to as fan-in, wafer-level package (WLP), the process for adding a metalized redistribution layer (RDL) connecting the original wire-bond lands to an array-configured terminal feature is accomplished while the die elements remain in the original silicon-based wafer format (Figure 1). 

While the majority of the semiconductors selected for face-down interconnect can utilize the RDL processes noted, an expanding number of small-outline, very-high I/O, silicon-based processors are really not suited for conventional fan-in RDL processing. 
 
Fan-out, Wafer-level Packaging (FOWLP)
The most practical solution for mounting and interconnecting very-high I/O, small-outline die to a substrate or PCB is to expand the terminal pattern outward. The process commonly utilizes a prepared silicon wafer base with metalized RDL designed to mount and interconnect the higher density die element to an array-configured terminal feature is outside the perimeter of the die. Metalization provided on the silicon wafer base redistributes the terminal features on each die to a pattern of plated micro-via holes that interfaces with metalized land pattern features on the opposite surface of the wafer (Figure 2). 
Solberg_fig2_0520.jpg
The die elements terminated on the wafer’s upper surface are frequently encased with a polymer mold compound followed by solder ball or bump terminal formation, marking,  
and singulation to enable unit-level electrical testing. 
 
Fan-out, Panel-level Packaging (FOPLP)
The semiconductor package development specialists are always striving to find solutions for improving manufacturing efficiency and trim manufacturing costs. Although the FOWLP process has proved robust and reliable, the cost associated with silicon-based interposer fabrication has been a primary roadblock. In the effort to trim overall packaging expense, a number of alternative packaging methodologies have emerged. Both independently and through consortia between academia and industry, several viable solutions have evolved that provide the same fan-out interface without the need for a silicon wafer as a base. 
 
Panel-level package development utilizing alternative, lower-cost base materials actually began prior to 2016 to address several high volume market segments. By 2019, four prominent supply sources in Asia—Powertech, Samsung, and Nepes—had already achieved volume-manufacturing capability followed by ASE Group beginning production in early 2020. The timetable for additional offshore and domestic companies’ availability of FOPLP in volume is forecast for 2021 and 2022. 
 
FOWLP vs. FOPLP
When compared to the silicon-based FOWLP, developers implementing the panel-configured process have realized significant cost savings, greater process efficiency, and the economies of scale. Equating the high material cost of silicon wafers to the significantly lower-cost panel material is a key issue, but the greater die population potential for panel-level processing has proved most beneficial. 
 
In regard to establishing standards for the basic panel structure, several manufacturers and material supplier members of SEMI (Semiconductor Equipment and Materials International) 3D Packaging and Integration Technical Committee have developed SEMI 3D20-0719, which is a specification for panel characteristics for panel-level packaging (PLP) applications. The organization’s position is that “standards increase industry efficiency by reducing or eliminating duplication of efforts, help to define new markets, and promote competition by lowering barriers to entry.”
 
The purpose and scope for the SEMI PLP specification were written to include four process-compliant base materials for carrier panels and establish standard panel dimensions. Revision A of the document (currently submitted for member approval) establishes two standard panel sizes: 510 mm x 515 mm (~ 20” x 20.3”) and 600 mm x 600 mm (~ 23.6” x 23.6”). The four optional base materials noted for carrier panel preparation are glass, silicon, ceramic, and metal; however, silicon and ceramic materials have a significantly higher material cost. 
 
The semiconductor-packaging specialists will select the material and panel size that will best meet their particular assembly, molding system, and plating process capability. In regard to panel size, the half-panel may be more suitable for processing within the commercial circuit board manufacturing environment while a quarter-panel size will likely be most compatible with semiconductor wafer processing specialists currently utilizing systems configured to handle the 300 mm silicon wafer format.
 
In a presentation by Fraunhofer IZM[1] at a recent International Electronics Commission (IEC) standards meeting in Japan, the speaker noted several key drivers supporting FOPLP technology:  

  • Reduced overall package form factor 
  • A thinner package profile
  • Improved electrical performance 
  • Enhanced thermal management 
  • The potential for greater component integration and design flexibility 

The packaging process variations described in the Fraunhofer presentation primarily focused on a mold-first procedure where the singulated die elements are placed, with the active surface face-up or face-down, onto the carrier panel that is pre-coated with an adhesive. 
 
Mold-first FOPLP
Following die placement, the populated  
carrier panel is overmolded with a reinforced polymer compound, fully encasing all die  
elements. The material selected for the carrier panel must closely match the CTE of the silicon-based die elements (2.3 ppm/K) to minimize the occurrence of die shift during the mold cure process, 

  • Face-down FOPLP: After mold cure, the encased die elements are separated from the carrier panel exposing the active surface of the die elements. Surface metalization follows with pattern plating from the die terminal sites to a fan-out terminal pattern (Figure 3a). 
  • Face-up FOPLP: The overmolded die elements mounted in the face-up orientation (Figure 3b) is somewhat more complex because it requires the removal of the polymer mold material to expose the terminal features for surface metalization and circuit pattern plating typical of that described above.

Solberg_fig3_0520.jpg
The final process sequence for both process variations includes terminal formation (typically a solder-compatible alloy ball or bump), marking, saw or laser singulation, and package-level electrical test. 
 
For very fine pitch (>3.0 mm) applications, the developer may employ a secondary selective plating process to form raised, solid copper terminals. The so-called “micro pillar” is significantly smaller in diameter than the ball or bump variations, enabling a considerably narrower ( 
Solberg_fig4_0520.jpgMultiple-die FOPLP
Other process variations have naturally evolved, including multiple-die configurations. The benefit of clustering and interconnecting two or more associated heterogeneous or homogenous semiconductor die within the confines of a single package outline enables very close coupling and the potential for enhanced electrical performance (Figure 4). 
 
The target package outline for a broad number of wearable and wireless products is 100 mm2 to 140 mm2. Ideally, the die elements selected for both single and multiple-die applications will be able to achieve equivalent finished package outline goals while maintaining the uniform terminal pattern required for efficient PCB-level circuit routing. Although the interconnect design process may initially remain within the package developer organizations, PCB design specialists will likely have the opportunity to contribute their talents as well, especially in developing the multiple-die FOPLP configurations. 
 
Design Rules for FOPLP
In regard to design rules for single and multiple-die package applications, those currently familiar or becoming familiar with high-density additive and semi-additive circuit design criteria will be prepared to put their talents to good use. It’s really a matter of scaling. The design guidelines furnished in Table 1 illustrate the expectations for interconnecting semiconductor die in the FOPLP format.
 
Because process capabilities will often vary between one supplier or another, the circuit density and feature sizes noted in Table 1 may be more or less than those factors shown. Before beginning the development of the fan-out circuit interconnect pattern, the designer is advised to confirm compliance with the manufacturer’s imaging and plating capability.

Solberg_fig5_0520.jpg
 
Qualification Testing
With shorter development cycle time and more frequent introduction of new package technologies, a comprehensive qualification methodology will remain paramount in order to identify reliability weaknesses during the qualification of new package variations and material sets. A study by members of iNEMI (International Electronics Manufacturing Initiative) consortia[2] concluded that “New integrated circuit package technologies can be qualified using procedures and test conditions based on experience with similar technology previously qualified.” 
 
For example, semiconductor package developers are currently applying established JEDEC standards that basically require the end-product to be subjected to three solder reflow cycles at 260°C for preconditioning followed by 1,000 cycles through temperatures that range between –40°C and +125°C, as well as a highly accelerated temperature and humidity stress test (HAST) lasting 96 hours at 121°C with 85% relative humidity. Some experts, however, are concerned that current test standards may not identify reliability risks for all commercial-use environments. The iNEMI study noted, “While previous experience is important to consider, it cannot be the only criterion and relying too much on past experience may result in overlooking new failure modes and/or new wear-out mechanisms.”
 
In regard to package manufacturing process refinement, reaching satisfactory levels of throughput while maintaining quality objectives are not trivial issues. Developers have had to overcome a number of obstacles for each process variation. Matters that needed to be resolved include the selection of the most suitable carrier panel material, achieving precise die placement capability, dealing with mold material shrinkage and die shifting during the mold curing process, overcoming panel warping during the metalization process, and defining the most robust die thickness and mold cap thickness ratio.   
 
References
1. Dr. Tanja Braun, “Status FOPLP,” Fraunhofer IZM, Germany.
2. C. Grosskopf, F. Xue, D. Locker, S. Thomas, J. Zheng, & M. Tsuriya, “Benchmarking of Qualification Methodologies for New Package Technologies and Materials,” 2019  
International Conference on Electronics Packaging (ICEP), Niigata, Japan, 2019, pp. 1–6.
 
This column originally appeared in the May 2020 issue of Design007 Magazine.

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