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Material Selection for SERDES Design

Many challenges face the engineer and PCB designer working with new technologies. For SERDES--high-speed serial links--loss, in the transmission lines, is a major cause of signal integrity issues. Reducing that loss, in its many forms, is not just a matter of reducing jitter, bit error rate (BER) or inter-symbol interference (ISI). Materials used for the fabrication of the multilayer PCB absorb high frequencies and reduce edge rates thus putting the materials selection process under tighter scrutiny. This column will look at the factors that must be taken into account, in the selection process, and provides some options for PCB designers.

The ideal transmission line model has properties distributed along its length. A physical transmission line can be approximated by describing sections of signal and return path as a loop inductance along its length. The simplest equivalent circuit model has a series of capacitors separated by loop inductors. There are also small series resistors with the inductors and shunt resistors across the capacitors which we assume are negligible. If I recall from Circuit Theory 101, this looks very similar to a low-pass filter, which of course attenuates high frequencies.

The Fourier Theorem states that every function can be completely expressed as the sum of sine and cosine of various amplitudes and frequencies. The Fourier series expansion of a square wave is made up of a sum of odd harmonics. If the waveform has an even mark to space ratio then the even harmonics cancel. Also, as the frequency increases, the amplitude decreases. **Read the full column here**.*Editor's Note: This column originally appeared in the September 2013 issue of The PCB Design Magazine.*