Beyond Design: Stackup Planning, Part 3


Reading time ( words)

Following on from the first Stackup Planning columns, this month’s Part 3 will look at higher layer-count stackups. The four- and six-layer configurations are not the best choice for high-speed design. In particular, each signal layer should be adjacent to, and closely coupled to, an uninterrupted reference plane, which creates a clear return path and eliminates broadside crosstalk. As the layer count increases, these rules become easier to implement but decisions regarding return current paths become more challenging.

Given the luxury of more layers:

  • Electromagnetic compliancy (EMC) can be improved or more routing layers can be added.
  • Power and ground planes can be closely coupled to add planar capacitance, which is essential for GHz plus design.
  • The power distribution networks (PDNs) can be improved by substituting embedded capacitance material (ECM) for the planes.
  • Multiple power planes/pours can be defined to accommodate the high number of supplies required by today’s processors and FPGAs.
  • Multiple ground planes can be inserted to reduce the plane impedance and loop area.

Although power planes can be used as reference planes, ground is more effective because local stitching vias can be used for the return current transitions, rather than stitching decoupling capacitors which add inductance. This keeps the loop area small and reduces radiation. As the stackup layer count increases, so does the number of possible combinations of the structure. But, if one sticks to the basic rules, then the best performing configurations are obvious.

Figure 1 illustrates the spreading of return current density across the plane above and below the signal path. At high frequencies, the return current takes the path of least inductance. As the frequency approaches a couple of hundred MHz, the skin effect forces the return current to the surface (closest to the signal trace).

I previously mentioned that it is important to have a clearly defined current return path. But it is also important to know exactly where the return current will flow. This is particularly critical with asymmetric stripline configurations where one signal layer is sandwiched between two planes as in Figure 2. Now obviously, if the distance to the closest plane (h1) is the same distance as the far plane (h2) then the return current distribution will be equal on each plane (given the same inductance for each path). However, in order to force the current onto the ground (GND) plane of an unbalanced stripline configuration, h2 needs to be at least twice h1, and three times is better.

To read this entire column, which appeared in the August 2014 issue of The PCB Design Magazine, click here.

Share

Print


Suggested Items

Just Ask Happy: Two-Layer Low-Speed PCBs

07/03/2020 | I-Connect007 Editorial Team
We asked for you to send in your questions for Happy Holden, and you took us up on it! The questions you've posed run the gamut, covering technology, the worldwide fab market, and everything in between. Enjoy.

Just Ask Happy: Routing BGAs With High-Speed Diff Pairs

06/25/2020 | I-Connect007 Editorial Team
We asked for you to send in your questions for Happy Holden, and you took us up on it! The questions you've posed run the gamut, covering technology, the worldwide fab market, and everything in between. Enjoy.

Book Excerpt: Signal Integrity by Example

06/11/2020 | I-Connect007 Editorial Team
Editor's note: The following is an excerpt from "The Printed Circuit Designer's Guide to... Power Integrity by Example," written by Fadi Deek of Mentor, a Siemens Business. Deek explores how to reach effective design solutions and make strong engineering tradeoffs through analysis techniques, best design principles, and software tools to achieve accurate simulations and measurements.



Copyright © 2020 I-Connect007. All rights reserved.