Target Condition: Are Autorouters Friend or Foe?
Fresh PCB Concepts: Assembly Challenges with Micro Components and Standard Solder Mask Practices
Elementary Mr. Watson: Retro Routers vs. Modern Boards—The Silent Struggle on Your Screen
Mentor Webinar May 5: Ensuring DDR4 Performance at Intended Data Rate
April 23, 2020 | Mentor, a Siemens businessEstimated reading time: 1 minute
DDR interfaces have many signal integrity and timing requirements that need to be guaranteed between multiple signal groups. Conformance to the requirements should be verified before a board is fabricated to reduce the chance of prototype spins. Traditionally, designers have relied on dedicated SI experts to perform this task or laid out boards based on manufacturer’s guidelines and skipped post-route verification entirely, hoping to avoid problems in the lab. Increasing data rates have pushed DDR operating margins to the point where simply following physical design rules is no longer enough to ensure that a design will work as intended.
This webinar by Mentor, a Siemens business, will be held twice on May 5, 2020: from 2-3 PM London time (UTC+1), and 2-3 PM Eastern time in the US. Presenter Min Maung will discuss the different electrical requirements associated with DDR designs and show how board and system designers can use HyperLynx to perform post-route verification themselves, helping free up scarce SI experts to focus on their company’s most challenging analysis problems.
What Attendees Will Learn
- DDR electrical requirements for signal integrity and timing
- Why “routing by the rules” isn’t enough anymore
- Why JEDEC specifications only give you half of the information you need
- How controller/DRAM configuration affects routing requirements
- How to use HyperLynx post-route verification to optimize margins for designs as routed
Who Should Attend
- PCB/system designers
- Engineering managers
- Signal integrity specialists
- PCB layout designers
To register for this web seminar, click here.
Share on:
Suggested Items
DownStream Acquisition Fits Siemens’ ‘Left-Shift’ Model
06/26/2025 | Andy Shaughnessy, I-Connect007I recently spoke to DownStream Technologies founder Joe Clark about the company’s acquisition by Siemens. We were later joined by A.J. Incorvaia, Siemens’ senior VP of electronic board systems. Joe discussed how he, Rick Almeida, and Ken Tepper launched the company in the months after 9/11 and how the acquisition came about. A.J. provides some background on the acquisition and explains why the companies’ tools are complementary.
Elementary Mr. Watson: Retro Routers vs. Modern Boards—The Silent Struggle on Your Screen
06/26/2025 | John Watson -- Column: Elementary, Mr. WatsonThere's a story about a young woman preparing a holiday ham. Before putting it in the pan, she cuts off the ends. When asked why, she shrugs and says, "That's how my mom always did it." She asks her mother, who gives the same answer. Eventually, the question reaches Grandma, who laughs and says, "Oh, I only cut the ends off because my pan was too small." This story is a powerful analogy for how many PCB designers approach routing today.
Siemens Turbocharges Semiconductor and PCB Design Portfolio with Generative and Agentic AI
06/24/2025 | SiemensAt the 2025 Design Automation Conference, Siemens Digital Industries Software today unveiled its AI-enhanced toolset for the EDA design flow.
Cadence AI Autorouter May Transform the Landscape
06/19/2025 | Andy Shaughnessy, Design007 MagazinePatrick Davis, product management director with Cadence Design Systems, discusses advancements in autorouting technology, including AI. He emphasizes a holistic approach that enhances placement and power distribution before routing. He points out that younger engineers seem more likely to embrace autorouting, while the veteran designers are still wary of giving up too much control. Will AI help autorouters finally gain industry-wide acceptance?
Beyond Design: The Metamorphosis of the PCB Router
06/18/2025 | Barry Olney -- Column: Beyond DesignThe traditional PCB design process is often time-consuming and labor-intensive. Routing a complex PCB layout can consume up to 30% of a designer’s time, and addressing this issue is not straightforward. We have all encountered this scenario: You spend hours setting the constraints and finally hit the Go button, only to be surprised by the lack of visual appeal and the obvious flaws in the result.