Trouble in Your Tank: A Process Engineer’s Guide to Advanced Troubleshooting, Part 2


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Editors note: Click here for Part 1 of this column.

Etching-Related Defects, or so It Seems
In my last column, I presented issues that were found at final assembly. However, the defects that manifested themselves after the boards were assembled had their genesis in electrolytic copper plating. In this month’s edition, I will discuss two interesting technical problems. The first defect I will present is the case of circuit open or etch-out, which will also include circuit width reduction related to undercut. The second defect relates to extraneous copper remaining on the board. Both issues illustrate the complex nature of PWB troubleshooting and defect analysis.  

Most process problems that appear during the etching stage of printed circuit production can be traced to one of two general areas. The most common and obvious cause of etching problems is the etching equipment itself, either through component failure (spray nozzles, pressures) or mis-adjustment, including conveyor speeds. 

The second most common cause during the etching step is with problems that occur during prior processing steps but are not detected until the boards are processed through the etcher. One example is resist scum left on the board during the stripping of a plating resist, which can cause uneven etching to occur. 

Another factor relates to the control or lack of control related to the chemical operating parameters. Carano_fig1_0720.jpgThese are just a few of the possibilities that will be presented in future editions of “Trouble in Your Tank.” For the purposes of this month’s column, the main defects to be discussed are the etched-out circuit trace and extraneous copper remaining after etching.
 
Etched-Out Circuit Trace
One of the most disconcerting issues related to bare board fabrication is to find an opening in one or more of the circuit traces after etching (Figure 1).

Carano_fig2_0720.jpgOf course, this defect did not manifest itself until after the inner layer etching step was completed. There are several possibilities related to the root cause of this defect. Figure 2 shows a partial etch-out of the circuit trace.

It is not likely the issue was caused by the etching process since the areas of partial etch-outs were sporadically seen on the panel. The most likely causes for the defect relates to surface preparation of the copper surface and the potential for resist lifting, allowing the etchant to gain access to the underlying copper. Essentially during the resist lamination process, resist did not completely conform to the copper surface. Remaining moisture on the panel may have vaporized, allowing the resist to blister at that point. In addition, when you investigate the glass weave texture related to the copper foil you see that a heavy glass weave may have negatively impacted the adhesion of the photoresist at that point. 

Extraneous Copper
Now for something completely different. The view of the layer in Figure 3 shows excess copper that remained after etching (this is an inner layer).
Carano_fig3_0720.jpgIn broad terms, this is clearly a develop-etch-strip (DES) issue. However, do not discount concerns with imaging. First, as part of the troubleshooting protocol, consider the actual etching operation as a starting point. At first glance, the panel is under etched, but why? Check the following variables in the etching system:

  • Conveyor speed too fast
  • Temperature of etching solution too low
  • Spray pressures have dropped for any number of reasons, including plugged spray nozzles
  • Inadequate replenishment of required chemical additives

The last bullet point requires a deeper dive, depending on what final etching process is in use (cupric chloride or alkaline ammoniacal). The specific features of these two processes will be presented in a future column. 
 
After reviewing and making any adjustments in the etching process, one should revert to the developing, surface prep, and imaging processes. Clearly, there are spots of copper remaining on the inner layer. One is then able to discern extraneous copper near the edge of the traces. It would be prudent to investigate lam-pre-cleaning, resist lamination, hold times, exposure, and development. For now, the focus will be on development.
 
Underdevelopment of Resist
Underdevelopment of resist will leave residual resist on the surface of the copper where it acts as an etch resist. Certainly, resist film thickness will play a role. It is reasonable to conclude that the remaining residues are easily able to inhibit the etching reaction. There are several possible conditions that are the potential root cause of the unetched copper:

  • Operating temperature of the developer is too low: verify the temperature gauge reading periodically with a hand thermometer.
  • Time in the developer is too short: while this is rare in conveyorized modules, it is possible. Use a stopwatch or timer to gauge time in the developer.
  • Has the breakpoint of the resist changed, meaning the resist appears to be breaking or is being cleaned off later in the chamber? Perhaps additional time is required. Additional time in the developer is needed to improve the breakpoint (Note: A late breakpoint may cause incomplete development in areas with poor mass transfer or poor spray impact, typically at the bottom of narrow resist channels. Excess copper will be seen here especially between  
narrowly spaced traces).
  • Low developer concentration: Check the pH. Effective development is seen between a pH of 10.4–10.8 for most fully aqueous resists.

Regardless, if the developing operation is controlled with an automated feed and bleed system tied to pH, this should not be an issue. However, it does not hurt to spot check the pH and concentrations of the carbonate. 
 
Finally, be cognizant of resist locking onto the surface. This would make developing more difficult. More on this when lamination and imaging are presented in a future column.  
 
This column originally appeared in the July 2020 issue of PCB007 Magazine.

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