Lattice Shrinks Design Footprint, Cost with Single Wire Aggregation IP Solution


Reading time ( words)

Lattice Semiconductor Corporation, the low power programmable leader, announced a Single Wire Aggregation (SWA) IP solution for reducing overall system size and BOM cost in industrial, consumer, and computing applications. The solution is a quick, easy, and innovative way for developers to use low power, small form factor Lattice FPGAs to dramatically reduce the number of board-to-board and component-to-component connectors in their embedded designs to increase reliability and reduce overall system footprint and cost.

The connectors used to link circuit boards and modules in electronic systems are costly, take up valuable space in devices with tight form factors, and over time can degrade and negatively impact system reliability. Routing signals between multiple connectors on space-constrained circuit boards can create design challenges that increase overall time-to-market.

“Developers are always looking for innovative ways to simplify and accelerate the development of embedded systems, while still maintaining the lowest BOM cost possible. Our new SWA solution meets all three of these needs by reducing the number of connectors in a system,” said Hussein Osman, Market Segment Manager, Lattice. “The solution is a strong fit for both novice and expert FPGA developers. Its pre-configured bitstreams help those new to FPGA-based design quickly configure an SWA application without requiring HDL coding experience, while the solution’s support for expanded parameterization makes it easy for FPGA experts to combine the Lattice SWA bitstreams with their own HDL code.”

Featuring the extremely low power and small size Lattice iCE40 UltraPlus™ FPGA, the SWA solution provides the hardware and software developers require to implement a single wire interface capable of aggregating multiple common I/O (I2C, I2S, UART and GPIO) data streams between components and circuit boards in a system. 

Share

Print


Suggested Items

DARPA’s Drive to Keep the Microelectronics Revolution at Full Speed Builds Its Own Momentum

08/28/2017 | DARPA
To perpetuate the pace of innovation and progress in microelectronics technology over the past half-century, it will take an enormous village rife with innovators. This week, about 100 of those innovators throughout the broader technology ecosystem, including participants from the military, commercial, and academic sectors, gathered at DARPA headquarters at the kickoff meeting for the Agency’s new CHIPS program, known in long form as the Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies program.

Beyond Scaling: An Electronics Resurgence Initiative

06/05/2017 | DARPA
The Department of Defense’s proposed FY 2018 budget includes a $75 million allocation for DARPA in support of a new, public-private “electronics resurgence” initiative. The initiative seeks to undergird a new era of electronics in which advances in performance will be catalyzed not just by continued component miniaturization but also by radically new microsystem materials, designs, and architectures.

NASA Investigates Techniques for Cooling 3-D Integrated Circuits Stacked Like a Skyscraper

11/02/2015 | NASA
Future integrated circuitry is expected to look a lot like skyscrapers: units will be stacked atop one another and interconnects will link each level to its adjacent neighbors, much like how elevators connect one floor to the next. The problem is how do integrated-circuit designers remove heat from these tightly packed 3-D chips? The smaller the space between the chips, the harder it is to remove the heat.



Copyright © 2020 I-Connect007. All rights reserved.