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Current IssueCreating the Ideal Data Package
Why is it so difficult to create the ideal data package? Many of these simple errors can be alleviated by paying attention to detail—and knowing what issues to look out for. So, this month, our experts weigh in on the best practices for creating the ideal design data package for your design.
Designing Through the Noise
Our experts discuss the constantly evolving world of RF design, including the many tradeoffs, material considerations, and design tips and techniques that designers and design engineers need to know to succeed in this high-frequency realm.
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Our expert contributors clear up many of the miscommunication problems between PCB designers and their fab and assembly stakeholders. As you will see, a little extra planning early in the design cycle can go a long way toward maintaining open lines of communication with the fab and assembly folks.
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Design for Profitability: Avoiding Fabrication Issues and Minimizing Costly Revisions
July 31, 2013 | Mark Thompson, CID, Prototron CircuitsEstimated reading time: 1 minute
Note that I use the term “design for profitability,” or DFP, as opposed to any of the other acronyms such as DFM (design for manufacturability), DFT (design for test), or DFA (design for assembly). I’m taking this approach because it really all comes down to profit, doesn’t it?
Designers have the power to design profit into the board, or, conversely, inadvertently increase costs and remove profit from the PCB. In this article I am going to go over just a few of the challenges that fabricators routinely face and some typical solutions, especially solutions that can affect your bottom line.
I will start with DFM. Generally, this is the first stage for prototyping and DFM depends greatly on the capabilities of your chosen fab shop. Some designs are finished with autorouters after the critical traces have been hand-placed. It is at this point that unintended issues can arise between design and fab.
An example of this is same net-spacing violations where a track may “double back” near a surface mounted component, creating same-net spacing violations (Figure 1). Whereas the software does not see these as legit violations because they are same net, a fabricator knows that any features creating spaces below 0.003” can easily flake off at the image stage and create havoc elsewhere in the form of shorts. Edit time must be taken at the fab stage when these same-net spacing violations occur and the slivers eliminated. Some CAM software packages have a sliver fill option, but again this requires additional edit time at CAM.
Read the full article here.
Editor's Note: This article originally appeared in the March 2013 issue of The PCB Design Magazine.
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