-
- News
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueShowing Some Constraint
A strong design constraint strategy carefully balances a wide range of electrical and manufacturing trade-offs. This month, we explore the key requirements, common challenges, and best practices behind building an effective constraint strategy.
All About That Route
Most designers favor manual routing, but today's interactive autorouters may be changing designers' minds by allowing users more direct control. In this issue, our expert contributors discuss a variety of manual and autorouting strategies.
Creating the Ideal Data Package
Why is it so difficult to create the ideal data package? Many of these simple errors can be alleviated by paying attention to detail—and knowing what issues to look out for. So, this month, our experts weigh in on the best practices for creating the ideal design data package for your design.
- Articles
- Columns
- Links
- Media kit
||| MENU - design007 Magazine
Cadence’s Brad Griffin Digs Deep Into DDR
February 22, 2015 | Kelly Dack, I-Connect007Estimated reading time: 12 minutes

Guest Editor Kelly Dack stopped by the Cadence Design Systems booth at DesignCon 2015, where he sat down with Product Marketing Manager Brad Griffin to discuss Cadence’s advanced PCB design and signal integrity tools, and the company’s focus on DDR.
Kelly Dack: Brad, since you’re the product marketing director for Cadence Design Systems, I’d like to ask a few questions about your DDR products. But first, please give us a brief overview of DDR.
Brad Griffin: I’d be happy to. One of the main things with a computer is that it has memory and you can store data in that memory—that’s kind of what makes it a computing device. So they’ve been finding ways over the life of electronics to store and retrieve data faster out of memory. Somewhere around 2002, we came up with this idea of doubling the data rate in DDR memory, or double data rate memory. That was unique because basically, we clocked the data into the memory, both on the rising edge and on the falling edge of the clock. It was a clever way with the same sort of signaling to basically double the data rate speeds.
KD: Was there an organization involved? Was it standardized?
BG: That’s really good question. As of right now, there's a standard committee called JEDEC, and I'm going to assume they were in place back in the 2002 timeframe, but I’d have to go back and check. But obviously there's memory companies and they have to be able to plug-and-play with different controllers as they’re driving the memory, so there's probably always been a standard they’ve been marching toward. That process used to be a lot simpler. You’d be transferring data at maybe 100 megabits per second. You would send the data, clock it in, and it wasn’t nearly as complicated as it is now.
KD: So where has DDR come from, and where is it now?
BG: There was DDR2 and then DDR3, and probably 2015 is going to be the transition where most DDR3 designs go over to DDR4. Typically, this happens because the DDR4 memory will actually become less expensive than some of the DDR3 memory.
KD: What does that mean as far as the technology from a power standpoint as well as a data standpoint?
BG: The main difference from a technology standpoint from DDR3 to DDR4 is the speed. It basically just gets faster. So any application you have in the computer that’s run with DDR4 memory will make for a faster computer than one running with DDR3. One of the exciting things that has migrated probably over the last five to seven years is this new version of DDR called LPDDR, which stands for low power. That’s been something primarily used in mobile devices because you certainly don’t want your cell phone to run out of power in the middle of the day.
KD: With this reference to power, if I understand correctly, DDR came from a 2.5 V system and shrunk to 1.8 V and 1.5 V, and DDR4 is down at a little over 1 V. That seems really low already, so where will the LPDDR take us?
BG: If you can believe it, the LPDDR4 specification only has a 300 mV swing, so it's really low. That means that for signal integrity and power integrity engineers, there's really very little margin left. We said there was very little margin left when it was 1.5 V, and now we’re down to 300 mV; this very small swing of data means that your signals have to be clean and your power planes have to basically be stable. Because then you have to have a power/ground bounce associated with simultaneous switching signals. It’s going to basically make it so that you're not going to meet the signal quality requirements that JEDEC puts in place for LPDDR4. So designs are getting really interesting. What we’re excited about this year at DesignCon are the things we’ve been putting into our tools to enable designers to validate that they've done everything they need to do to meet the LPDDR4 requirements.
Page 1 of 3
Suggested Items
Microchip Expands Space-Qualified FPGA Portfolio with New RT PolarFire® Device Qualifications and SoC Availability
07/10/2025 | MicrochipContinuing to support the evolving needs of space system developers, Microchip Technology has announced two new milestones for its Radiation-Tolerant (RT) PolarFire® technology: MIL-STD-883 Class B and QML Class Q qualification of the RT PolarFire RTPF500ZT FPGA and availability of engineering samples for the RT PolarFire System-on-Chip (SoC) FPGA.
Infineon Advances on 300-millimeter GaN Manufacturing Roadmap as Leading Integrated Device Manufacturer (IDM)
07/10/2025 | InfineonAs the demand for gallium nitride (GaN) semiconductors continues to grow, Infineon Technologies AG is poised to capitalize on this trend and solidify its position as a leading Integrated Device Manufacturer (IDM) in the GaN market.
Bell to Build X-Plane for Phase 2 of DARPA Speed and Runway Independent Technologies (SPRINT) X-Plane Program
07/09/2025 | Bell Textron Inc.Bell Textron Inc., a Textron Inc. company, has been down-selected for Phase 2 of Defense Advanced Research Projects Agency (DARPA) Speed and Runway Independent Technologies (SPRINT) X-Plane program with the objective to complete design, construction, ground testing and certification of an X-plane demonstrator.
2025 ASEAN IT Spending Growth Slows to 5.9% as AI-Powered IT Expansion Encounters Post-Boom Normalization
06/26/2025 | IDCAccording to the IDC Worldwide Black Book: Live Edition, IT spending across ASEAN is projected to grow by 5.9% in 2025 — down from a robust 15.0% in 2024.
DownStream Acquisition Fits Siemens’ ‘Left-Shift’ Model
06/26/2025 | Andy Shaughnessy, I-Connect007I recently spoke to DownStream Technologies founder Joe Clark about the company’s acquisition by Siemens. We were later joined by A.J. Incorvaia, Siemens’ senior VP of electronic board systems. Joe discussed how he, Rick Almeida, and Ken Tepper launched the company in the months after 9/11 and how the acquisition came about. A.J. provides some background on the acquisition and explains why the companies’ tools are complementary.