DDR4: Not Your Grandfather’s DDR


Reading time ( words)

A long time ago, when DDR first came out, some of you may remember that it was difficult to design the interface. In my old board design team, we simulated the interface quite a bit to make sure that the system would function when the boards came back.

Then of course, the “been-there-done-that” attitude set in, and DDR became a design-by-numbers interface to push the schedule. Then came DDR2, which had many similarities to DDR.  By the time DDR3 came out, many people didn’t even bother to simulate the setups at some of the slower speeds. They’re largely leveraged from a previous design, so why bother?

And then comes DDR4.  This is the new guy in town who you can sense is a bit different. Questions come up:

  • What, you don’t have a fixed Vref? 
  • You’re going to have a new threshold every time you power up? Then how do you know whether you’re the signal is a 1 or a 0 if I don’t know what the threshold is beforehand? 
  • What do you mean you’re going to flip all the bits?

Then maybe it starts to sink in:

Maybe I should simulate this. So, just how good are the IBIS models for this anyway?  Can I trust them at these higher speeds?

nitinb0215-1.png

These are many of the questions we answered, along with our partners at Fujitsu and Micron, in the paper that has was nominated at DesignCon for a best paper award: DDR4 Board Design and Signal Integrity Verification Challenges

In the first half of the paper, we discuss the details of DDR4.  What exactly are Pseudo-Open Drain (POD) and Data-Bit Inversion (DBI), and why the Vref is so dodgy?  It will give you good background information about how DDR4 is different from DDR3.

In the second half, we compare the simulation results of a large setup between the older IBIS 4.2 spec, the newer IBIS 5.0 spec, and a transistor level Spice model.  Spoiler alert: the IBIS 5.0 results very closely match the transistor level Spice models – at a small fraction of the time needed to simulate.

nitinb0215-2.jpg

If you are designing a DDR4, and would like to confirm your board, this paper is a helpful reference in deciding what needs to be analyzed before and after releasing the board.

Download your copy of the paper here.

Share




Suggested Items

I-Connect007 Editor’s Choice: Five Must-Reads for the Week

01/20/2023 | Andy Shaughnessy, Design007 Magazine
We’re in the middle of show season, and it certainly “shows.” Thank you very much. I’m here all week. Don’t forget to tip your wait staff. This week, we published a variety of articles, columns, and news items, and much of it centered on trade shows. Technical Editor Dan Feinberg brings us a report from CES 2023. IPC announced the winners of the Best Technical Paper awards for IPC APEX EXPO 2023. And we have an interview with Altium’s Rea Callender about the company’s educational efforts at APEX and around the globe.

Altium Focuses on Design Education

01/16/2023 | I-Connect007 Editorial Team
Altium keeps its eyes on the designers of the future. The company has been working with colleges and universities for years, providing free seats of Altium Designer for the next generation of PCB designers and design engineers. At IPC APEX EXPO 2023, Altium will be providing software for the finalists in the IPC Design Competition just as it did last year. They offer a variety of other educational programs as well, including Upverter classes and a design competition that aims to address environmental change. Here, Rea Callender, Altium’s VP of education, discusses its educational programs and plans for the week of the show.

The Battle of the Boards

01/12/2023 | Patrick Crawford, IPC
Last year, IPC held its first-ever design competition at IPC APEX EXPO in San Diego. PCB designers from around the world competed in a series of heats during the months before the show, culminating in a showdown on the show floor between the top three finalists. Rafal Przeslawski, now with AMD, took home the top prize last year. This year, the competition is back for its sophomore year. I asked Patrick Crawford, manager of design standards and related programs for IPC, to “layout” the details on the design contest, including lessons learned in 2022 and what’s new for the 2023 competition.



Copyright © 2023 I-Connect007 | IPC Publishing Group Inc. All rights reserved.