-
- News
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueOpportunities and Challenges
In this issue, our expert contributors discuss the many opportunities and challenges in the PCB design community, and what can be done to grow the numbers of PCB designers—and design instructors.
Embedded Design Techniques
Our expert contributors provide the knowledge this month that designers need to be aware of to make intelligent, educated decisions about embedded design. Many design and manufacturing hurdles can trip up designers who are new to this technology.
Manufacturing Know-how
For this issue, we asked our expert contributors to share their thoughts on the absolute “must-know” aspects of fab, assembly and test that all designers should understand. In the end, we’re all in this together.
- Articles
- Columns
Search Console
- Links
- Events
||| MENU - design007 Magazine
OC Designers Council Event to Focus on SI Routing Guidelines Nov. 18
November 11, 2015 | IPC Designers Council, Orange Co. ChapterEstimated reading time: 1 minute
What: Orange County chapter of the IPC Designers Council "Lunch 'n' Learn" Meeting
Date: Wednesday November 18, 2015
Time: 11:30 am - 1:30 pm
Where: Harvard Athletic Park multi-purpose room – Irvine
Topic: PCB Routing Guidelines for Signal Integrity and Power Integrity. Also includes recommendations to improve high-speed performance of any design at any data rate Speaker: Chris Heard, signal integrity engineering consultant, CSH Consulting LLC
Speaker Chris Heard has been deeply involved with signal and power Integrity for over 25 years and has a wealth of knowledge to share. Chris’s presentation will cover a list of "Do’s and Don'ts" regarding the most commonly seen routing practices that have a big impact on signal integrity. His presentation will cover the importance and signal integrity’s impact on drill size, pad size, antipad size, ground plane overhang, transition vias, AC capacitors, skew compensation, backdrilling, blind vias, narrow vs. wide lines, and surface vs. inner layer routing. Use of leading simulation tools will be presented.
In his presentation on power integrity, Chris will cover voltage drop and impedance response vs. frequency for various power plane examples. The impact of various capacitor sizes and placement and the use of buried capacitor layers will be shown and discussed. The interaction and the understanding of these two disciplines are vital to success of the designer in achieving fully optimized designs. Don’t miss this opportunity to learn valuable tips from our expert speaker.
Reserve a spot on your calendar on Wednesday, November 18 from 11:30 am to 1:30 pm for this educational “Lunch ‘n’ Learn” meeting event.
Location:
Harvard Athletic Park (The multi-purpose room is at the SOUTH end of the athletic fields)
14701 Harvard Ave.
Irvine, CA 92606
Agenda:
Lunch served 11:30 - 11:50
Misc. Business 11:50 - 12:00
Presentation 12:00 - 1:15
Q & A discussion 1:15 - 1:25
Door prize raffle 1:25 - 1:30
Cost:
The cost to attend this "Lunch ‘n' Learn" event will be $10 at the door to help cover part of the lunch cost and room rental.
Please RSVP no later than noon Tuesday, November 17, 2015. There are now two ways to RSVP:
- Click here to RSVP
- Email your RSVP to terri_kleekamp@mentor.com
I look forward to seeing you there!
Scott McCurdy, Freedom CAD Services
President, IPC Designers Council Orange County chapter
www.ocipcdc.org
Cellphone: 714-425-3235
Email:scott.mccurdy@freedomcad.com
Suggested Items
ASMPT to Exhibit Smart Manufacturing at IPC APEX EXPO 2024
03/27/2024 | ASMPTWith its innovative, data-driven Intelligent Factory concept and a comprehensive hardware and software portfolio around SMT production, market and innovation leader ASMPT will be a major presence at the IPC APEX EXPO 2024, the industry’s main event in California.
Mycronic to Showcase More Versatile, High-productivity Assembly Solutions at IPC APEX EXPO 2024
03/27/2024 | MycronicMycronic, the leading Sweden-based electronics assembly solutions provider, will continue to respond to growing customer demand for high-flexibility, high-productivity solutions for zero-defect PCB assembly at IPC APEX EXPO 2024 in Anaheim, CA on April 9 - 11.
TRI Launches New Advanced Packaging 3D CT AXI Solution
03/26/2024 | TRITest Research, Inc. (TRI) proudly announces the launch of the SEMI 3D CT AXI solution, TR7600F3D SII Plus, marking a paradigm shift in precision and reliability for high-reliability electronics manufacturing, such as the Advanced Packaging Industry.
Blackfox Ready for IPC APEX EXPO 2024
03/26/2024 | Andy Shaughnessy, I-Connect007Blackfox Training Institute offers IPC-certified training for a myriad of PCB assembly techniques and standard certifications. With many technologists beginning to eye retirement, this training is at a premium. I recently spoke with Jamie Noland, director of training and education for Blackfox, about the company’s latest educational efforts, and his plans for the upcoming IPC APEX EXPO, where Blackfox will be exhibiting.
iNEMI/IPC White Paper on Complex Integrated Systems Highlights Future Technology and Manufacturing Ecosystem Needs
03/25/2024 | IPCToday’s system solutions combine more varied functionality, such as digital, analog, optical, micro-mechanical, etc., packed into smaller form factors. As a result, electronics manufacturing has to deliver increasingly complex integration of diverse technologies with system designs that blur the distinction between chip, package, board, and assembly.