-
-
News
News Highlights
- Books
Featured Books
- pcb007 Magazine
Latest Issues
Current IssueThe Hole Truth: Via Integrity in an HDI World
From the drilled hole to registration across multiple sequential lamination cycles, to the quality of your copper plating, via reliability in an HDI world is becoming an ever-greater challenge. This month we look at “The Hole Truth,” from creating the “perfect” via to how you can assure via quality and reliability, the first time, every time.
In Pursuit of Perfection: Defect Reduction
For bare PCB board fabrication, defect reduction is a critical aspect of a company's bottom line profitability. In this issue, we examine how imaging, etching, and plating processes can provide information and insight into reducing defects and increasing yields.
Voices of the Industry
We take the pulse of the PCB industry by sharing insights from leading fabricators and suppliers in this month's issue. We've gathered their thoughts on the new U.S. administration, spending, the war in Ukraine, and their most pressing needs. It’s an eye-opening and enlightening look behind the curtain.
- Articles
- Columns
- Links
- Media kit
||| MENU - pcb007 Magazine
Kelvin Characterization to Accurately Predict Copper Thickness
July 1, 2019 | Article by Brandon Sherrieb, Integrated Test CorporationEstimated reading time: 3 minutes

Background
A few years ago at Integrated Test Corporation, we found that the reaction plan for void fallout at electrical test was ineffective and not standardized. Like many PCB manufacturing facilities (including a Sanmina shop that I used to work at), the reaction plan consisted of cross section analysis to determine the void type.
Then, based on the type of void, we would either thermal stress and cross section coupons from passing boards or process passing boards through reflow simulation and retest electrical continuity for disposition.
In addition to these reaction plans, another that I have experienced at Sanmina included one where circuit boards would be processed numerous times through a micro-etch process and retested for electrical continuity if voiding was found within unfilled holes. If the panels withstood that, they should be okay, right? Unfortunately, none of these disposition methods are robust enough to ensure that vias with marginal connection are caught before shipment. As we all know, a few holes within a coupon is hardly representative of the thousands of holes within a circuit board, and processing production orders through a reflow simulation or micro-etch before assembly will negatively impact the life of that PCB.
Therefore, the only way to ensure that marginal products are not being shipped to the customer is to perform an electrical test on those suspect vias at a low enough resistance where minor differences between vias can be observed. A method that was evaluated and proven successful would be four-wire Kelvin testing; if characterized properly for your process, it can distinguish differences in copper thickness between holes. A failure discovered by this testing method is depicted in Figure 1.
Figure 1: Example of low copper discovered
At the time, Integrated Test Corporation did have Kelvin probes and a flying probe tester that was capable of performing the testing process. However, it had not been properly set up to accurately predict what the resistance measurements should be based on the aspect ratio of the via and the amount of copper in the hole.
The first few times the process was used, all that was accomplished was to indicate which holes had resistance measurements outside of the normal distribution of results. These were then sectioned, and it was found that they would have met the minimum copper criteria.
After a few instances of performing destructive analysis on nondiscrepant products, it was decided that this process required testing for proper characterization. A quick search of articles and white papers
yielded comprehensive descriptions of the process itself but not guides on how to set it up in production. Most of the papers available described building a baseline of resistance measurements with known good panels. Ultimately, the process that we desired was to accurately predict the resistance measurements based on drill aspect ratio and copper thickness. This would require a correlation between these measurements and a set of equations. These equations could then be used to set the maximum resistance specification during testing or to determine the copper thickness within plated through-holes without destructive analysis.
Characterization
At Integrated Test Corporation, very high aspect ratio vias are common in production. So, we decided to design a test panel that was 0.300” that could be drilled with coupons including 0.010”, 0.012”, 0.015”, and 0.020” vias to characterize the process for aspect ratios up to 30:1. For each diameter, via coupons were included that were copper plated with 0.0002”, 0.0004”, 0.0006”, 0.0008”, and 0.001”, respectively. To ensure that the proper amount of copper plating was deposited in the holes, boards were processed through many different plating cycles, covering and uncovering coupons with resist during each cycle.
This was found to be more cost-effective than building panels exclusively for each copper plating thickness. However, doing the characterization in this manner would simplify the plating and imaging operations.
To read the full version of this article which originally appeared in the June 2019 issue of PCB007 Magazine, click here.
Suggested Items
The Evolution of Picosecond Laser Drilling
06/19/2025 | Marcy LaRont, PCB007 MagazineIs it hard to imagine a single laser pulse reduced not only from nanoseconds to picoseconds in its pulse duration, but even to femtoseconds? Well, buckle up because it seems we are there. In this interview, Dr. Stefan Rung, technical director of laser machines at Schmoll Maschinen GmbH, traces the technology trajectory of the laser drill from the CO2 laser to cutting-edge picosecond and hybrid laser drilling systems, highlighting the benefits and limitations of each method, and demonstrating how laser innovations are shaping the future of PCB fabrication.
Day 2: More Cutting-edge Insights at the EIPC Summer Conference
06/18/2025 | Pete Starkey, I-Connect007The European Institute for the PCB Community (EIPC) summer conference took place this year in Edinburgh, Scotland, June 3-4. This is the third of three articles on the conference. The other two cover Day 1’s sessions and the opening keynote speech. Below is a recap of the second day’s sessions.
Day 1: Cutting Edge Insights at the EIPC Summer Conference
06/17/2025 | Pete Starkey, I-Connect007The European Institute for the PCB Community (EIPC) Summer Conference took place this year in Edinburgh, Scotland, June 3-4. This is the second of three articles on the conference. The other two cover the keynote speeches and Day 2 of the technical conference. Below is a recap of the first day’s sessions.
Preventing Surface Prep Defects and Ensuring Reliability
06/10/2025 | Marcy LaRont, PCB007 MagazineIn printed circuit board (PCB) fabrication, surface preparation is a critical process that ensures strong adhesion, reliable plating, and long-term product performance. Without proper surface treatment, manufacturers may encounter defects such as delamination, poor solder mask adhesion, and plating failures. This article examines key surface preparation techniques, common defects resulting from improper processes, and real-world case studies that illustrate best practices.
RF PCB Design Tips and Tricks
05/08/2025 | Cherie Litson, EPTAC MIT CID/CID+There are many great books, videos, and information online about designing PCBs for RF circuits. A few of my favorite RF sources are Hans Rosenberg, Stephen Chavez, and Rick Hartley, but there are many more. These PCB design engineers have a very good perspective on what it takes to take an RF design from schematic concept to PCB layout.