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Popular ICT platforms from well-known vendors can perform a wide variety of analogue, digital, powered, and unpowered tests to verify the integrity of electronic assemblies. In addition to basic opens and shorts testing, analogue test capabilities include resistor, capacitor, potentiometer, diode and transistor tests. They can also verify power rails, and can generate digital test vectors as well as analogue waveforms to check for circuit functionality.
The test coverage that can be achieved using a bed of nails fixture alone is becoming increasingly limited. The biggest problem here is that any component pins not extending through to the probed side of the assembly are not accessible to the fixture nails unless the individual nets connected to it are exposed via unmasked vias, attached thru-hole connectors, or test points. The process of adding test access for ICT increases the cost of design, layout, and manufacturing: extra vias, extra test points, and extra routing necessities all increase the overall complexity of the assembly. Physical test access is not free.
Boundary-scan, used in conjunction with fixture-based tests, can extend test coverage on boards where test access is limited, and is critical to providing powered-shorts, opens and corelogic testing. IEEE 1149.1 compliant boundary-scan devices have the capability of driving and measuring pin states without physical access to the pin using a tester probe. ICT vendors integrate boundary-scan capabilities developed in-house to provide basic scan functionality that is native to the test platform, but this is not without its drawbacks.
Flying probe testers can offer an alternative to ICT that eliminates some disadvantages such as the cost and lead times associated with bedof-nails test fixtures and the PCBA modifications they require. On the other hand, devices like BGAs with inaccessible pins restrict the coverage possible using ordinary flying probe testing. Augmenting flying probe with boundary-scan can help overcome this problem and delivers additional valuable benefits.
Test Without Touching
The native boundary-scan test capability of a system such as the Keysight 3070 ICT station is able to generate tests for boundary-scan devices connected to the boundary-scan chain. Testing non boundary-scan devices on nets connected to the boundary-scan chain is possible, using Keysight’s optional Silicon Nails tool. As the name suggests, Silicon Nails uses the scan capable IC in a boundary-scan chain to probe the pins of the connected non boundaryscan device. However, some amount of manual interaction may be required, particularly if any pin on the non boundary-scan device is not connected to a boundary-scan cell. The VCL (vector construction language) libraries assume that all pins on the target device are accessible. If this is not the case, Silicon Nails will not generate the test properly. The user must then modify the library to change the properties of non-accessible pins so that the Silicon Nails test can be generated. Similar modifications have to be made for every test that the system is unable to generate automatically. In contrast, writing test scripts can be straightforward with specialist external boundary-scan tools, especially when using a highlevel device-centric language. The system automatically generates test vectors at runtime that meet the stated requirements. Moreover, users can benefit from the increased capabilities of specialist equipment, such as advanced connection tests that are able to identify faults that more basic tests cannot detect, and can pinpoint the causes of any faults extremely accurately. Tests such as shorts, opens, pull-ups, pull-downs and interconnection testing can be performed automatically.
By combining specialist boundary-scan capabilities with ICT, users can take advantage of state-of-the-art boundary-scan functionality, such as automatic generation of tests for non boundary-scan devices. Test scripts are easy to write, particularly when using a high-level device-centric language that allows the test description to be abstracted from the detail of generating test vectors.
Editor's Note: This article originally appeared in the June 2015 issue of SMT Magazine.