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Current IssueThe Hole Truth: Via Integrity in an HDI World
From the drilled hole to registration across multiple sequential lamination cycles, to the quality of your copper plating, via reliability in an HDI world is becoming an ever-greater challenge. This month we look at “The Hole Truth,” from creating the “perfect” via to how you can assure via quality and reliability, the first time, every time.
In Pursuit of Perfection: Defect Reduction
For bare PCB board fabrication, defect reduction is a critical aspect of a company's bottom line profitability. In this issue, we examine how imaging, etching, and plating processes can provide information and insight into reducing defects and increasing yields.
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Just Ask Joe Fjelstad: The Exclusive Compilation
November 19, 2020 | I-Connect007 Editorial TeamEstimated reading time: 5 minutes

We asked for you to send in your questions for Joe Fjelstad, and you took us up on it! We know you all enjoyed reading these questions and answers, so we’ve compiled all of them into one article for easy reference. We hope you enjoy having another bite at the apple. And if you’d like to hear more from Joe, view his column series “Flexible Thinking.”
The Occam Process
Q: Is the Occam process an early version of chiplets, placing chips first in assembly?
A: There have been a number of speculative and prospective chip first package solutions over the last 15–20 or more years. GE, Intel, and others have shown ways of interconnecting chips in packages by plating and then socketing or surface mounting the resulting components on PCBs using solder as almost everything still is today.
Chiplets are a more recent manifestation where chips are tiled and interconnected in mosaic form around the edges using solder. Occam was envisioned as a way to eliminate solder from the manufacturing process by reversing the manufacturing process. That is, building a “component board” comprised ideally of packaged ICs, all having a common grid pitch for terminations and which have been tested and burned in. Circuits are then built up onto the component board as if it was a basic PCB substrate. The component board substrate can be of almost any material because soldering is not required. Aluminum is suggested because it is an excellent thermal conductor and has a CTE near that of copper. Having all components with a common grid makes routing very efficient, and layer counts can drop significantly. Because there is no soldering, there is no unintended thermal damage to components or assembly. With the reduced number of steps, the assemblies should be much less expensive.
The Land Warrior Project
Q: Was your Land Warrior project ever implemented?
A: The Land Warrior system was developed and fielded by a Pacific Consultants team of 40-some engineers and technicians (after winning a design competition against three top-tier military systems contractors). The contract was managed by Exponent. Approximately 100 systems were built and demonstrated in a war games exercise at Fort Polk in 2000. It exceeded all expectations. Land Warrior development has continued in one form or another since and has seen service in conflicts since 2001. The name Land Warrior was changed to Nett Warrior in 2010 to honor Medal of Honor winner Robert B. Nett. For more information, click here.
Optimum Thermal Via Farm Copper Plating
Q: What is the optimum copper plating thickness for thermal via farms?
A: The question is an important one, but it is not easy, or perhaps even possible, to provide a hard answer to the question as there are many variables to consider. How many vias? What is their pitch? What size (diameter and depth) are they? How much heat needs to be removed? Are they filled with copper or just hole-wall plated? Are they independent features or connected en masse to a copper plane? In a sense, the best answer is perhaps that they collectively resemble the extent possible a copper slug. I would suggest that some thermal modeling of the solution be performed beforehand.
That said, there are some interesting technologies being rolled out at the present time. One is from the Silicon Valley company, Kuprion, which has developed a nanoparticle “copper solder,” which appears worth considering as an alternative to plating vias.
Automotive Conformal Coatings
Q: Of all the various conformal coating materials available, what would you recommend for automotive electronics?
A: The question indicates knowledge that there are different conformal coating options out there. It is not really possible to pick a definitive solution without knowing more detail about the application specifics. In general, a conformal coating is used to seal the electronics from the environment, but there may be other demands/desires placed on the material in terms of “reworkability” and/or special environmental and/or chemical resistance requirements. I’d suggest creating a list of desired qualities and performance needs/requirements, along with ease of use, rework-ability and submitting them to the various vendors for their responses. The vendors can often serve as good and reliable resources for answering questions you might not have thought to ask.
Standardized Grid Designs
Q: Will standardized grid designs ever come to fruition?
A: I am old enough to know that once upon a time, the electronics industry actually had a standardized grid. It was 0.100”. It was the natural by-product of the fact that most early electronic packages were dual in-line packages (DIPs), and nearly all of the first DIPs had their leads on 100-mil pitch (the Soviets and Eastern Bloc nations went with 2.5 mm rather than 2.54 mm or 0.1 inches). It was a natural default, and 100-mil grid pitch design was common and the standard even today; think of hobbyist’s bread boards, which are on a 100-mil grid.
Those halcyon days were disrupted as pin counts rose, and surface-mount technology took the stage to help manage the explosion in package pin counts. Then there was the “80% rule” for package leads that took effect to provide a defined roadmap for following generation component lead pitch. Thus, today (ignoring inch-based devices), we have 2.5 mm, 2.0 mm, 1.5 mm, 1.25 mm, 1.0 mm, 0.8 mm, 0.65 mm, 0.5 mm, 0.4 mm, etc.
Area array technology offered the opportunity to return to a standard grid, but the 80% rule was applied instead, which is a great pity from my perspective. Instead, what might have been done is to agree on a common base grid pitch and depopulate to the pin count desired. Everything gets easier again—no more burning off layers of circuits to accommodate escapes and differing grid pitch components. It is an easy way to return to standardized grids. All that is necessary is for component packagers to offer every component with terminations on a standard grid. My suggestion is 0.5 mm because that is where component soldering yields start to fall off.
Is it possible to return to the standard grid? Absolutely. It is more a question of customer demand for such and package foundries’ willingness to do so. It could save billions of dollars annually, according to my back-of-the-napkin calculations.
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