Reducing Down to 1/3 of Thermal Resistance by WOW Technology for 3D DRAM Application

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Researchers at Tokyo institute of Technology (Tokyo Tech) presented a design guide for reducing 30% of thermal resistance for 3-dimensional (3D) stacked devices compared with the conventional ICs using solder bump joint structure. 

Researcher team led by Professor Takayuki Ohba at Tokyo Tech, ICE Cube Center, in collaboration with the WOW (Wafer-on-Wafer) Alliance2, an Industry-academic collaborative research organization consisting of multiple semiconductor related companies aiming for practical applications of 3D IC technology, demonstrated the thermal resistance of the 3D stacked device can be reduced down to less than 1/3 relative to the conventional one bonded by bump3 3D IC in Through-Silicon-Via (TSV) wiring4. Since semiconductor circuits are highly heat-generating bodies during operation, when heat is hard to be released, the temperature of the semiconductor results in highly rise, which leads to be a malfunction. The development of heat dissipation technology has been a big challenge. 

To address this challenge, Ohba and colleagues analyzed thermal properties in 3D IC using finite element method (FEM5) and thermal network calculation method. The study identified three main factors of thermal resistance; the interconnection layers, dielectric layers and organic layers in the conventional bump type device. Contrary to the bump type, the thermal performance of a bumpless 3D IC was almost 150 times better than that of a conventional IC at the same TSV density. The researchers demonstrated to reduce the total thermal resistance to 0.46 Kcm2/W, whereas the conventional method is 1.54 Kcm2/W. This suggests that the bumpless enables lower temperature rise and three to four times further DRAM stacking. 

Based on their demonstration experiments, the scientists will work toward practical use of large-capacity memory technology for mobile terminals and servers.