Ultra-Clean Fabrication Platform Produces Nearly Ideal 2D Transistors
May 20, 2019 | Columbia EngineeringEstimated reading time: 3 minutes

Semiconductors, which are the basic building blocks of transistors, microprocessors, lasers, and LEDs, have driven advances in computing, memory, communications, and lighting technologies since the mid-20th century. Recently discovered two-dimensional (2D) materials, which feature many superlative properties, have the potential to advance these technologies, but creating 2D devices with both good electrical contacts and stable performance has proved challenging.
Image Caption: A Hall-bar device structure (see inset) is wire-bonded to a 16-pin chip-carrier. The chip-carrier allows for extensive electrical characterization of the device at both low temperatures and high magnetic fields.
Researchers at Columbia Engineering report that they have demonstrated a nearly ideal transistor made from a two-dimensional material stack—with only a two-atom-thick semiconducting layer—by developing a completely clean and damage-free fabrication process. Their method shows vastly improved performance compared to 2D semiconductors fabricated with a conventional process, and could provide a scalable platform for creating ultra-clean devices in the future.
“Making devices out of 2D materials is a messy business,” says James Teherani, assistant professor of electrical engineering. “Devices vary wildly from run to run and often degrade so fast that you see performance diminish while you’re still measuring them.”
Having grown tired of the inconsistent results, Teherani’s team set out to develop a better way to make stable devices. “So,” he explains, “we decided to separate the pristine device from the dirty fabrication processes that lead to variability.”
As shown in this new study, Teherani and his colleagues developed a two-step, ultra-clean nanofabrication process that separates the “messy” steps of fabrication—those that involve “dirty” metallization, chemicals, and polymers used to form electrical connections to the device—from the active semiconductor layer. Once they complete the messy fabrication, they could pick up the contacts and transfer them onto the clean active device layer, preserving the integrity of both layers.
“The thinness of these semiconductors is a blessing and a curse,” says Teherani. “While the thinness allows them to be transparent and to be picked up and placed wherever you want them, the thinness also means there's nearly zero volume—the device is almost entirely surface. Because of this, any surface dirt or contamination will really degrade a device.”
Currently, most devices are not encapsulated with a layer that protects the surface and contacts from contamination during fabrication. Teherani’s team showed that their method can now not only protect the semiconductor layer so that they don't see performance degradation over time, but it can also yield high performance devices.
Teherani collaborated with Jim Hone, Wang Fong-Jen Professor of Mechanical Engineering, making use of the fabrication and analysis facilities of the Columbia Nano Initiative and the National Science Foundation-funded Materials Research Science and Engineering Center at Columbia. The team made the transferred contacts from metal embedded in insulating hexagonal boron nitride (h-BN) outside a glovebox and then dry-transferred the contact layer onto the 2D semiconductor, which was kept pristine inside a nitrogen glovebox. This process prevents direct-metallization-induced damage while simultaneously providing encapsulation to protect the device.
The fabrication process for transferred contacts that yield nearly ideal transistors. Transferred contacts prevent contamination and damage to the 2D semiconductor that occur during fabrication of conventional contacts.
Video on the differences between 2D and 3D materials
Video on the step-by-step nanofabrication of 2D material stacks
Now that the researchers have developed a stable, repeatable process, they are using the platform to make devices that can move out of the lab into real-world engineering problems.
“The development of high performance 2D devices requires advances in the semiconductor materials from which they are made,” Teherani adds. “More precise tools like ours will enable us to build more complex structures with potentially greater functionality and better performance.”
About Columbia Engineering
Columbia Engineering, based in New York City, is one of the top engineering schools in the U.S. and one of the oldest in the nation. Also known as The Fu Foundation School of Engineering and Applied Science, the School expands knowledge and advances technology through the pioneering research of its more than 220 faculty, while educating undergraduate and graduate students in a collaborative environment to become leaders informed by a firm foundation in engineering. The School’s faculty are at the center of the University’s cross-disciplinary research, contributing to the Data Science Institute, Earth Institute, Zuckerman Mind Brain Behavior Institute, Precision Medicine Initiative, and the Columbia Nano Initiative. Guided by its strategic vision, “Columbia Engineering for Humanity,” the School aims to translate ideas into innovations that foster a sustainable, healthy, secure, connected, and creative humanity.
Suggested Items
BEST Inc. Presents StencilQuik for Simplifying BGA Rework Challenges
04/02/2025 | BEST Inc.BEST Inc., a leader in electronic component rework services, training, and rework tools is thrilled to announce StencilQuik™ rework stencils. This innovative product is specifically designed for placing Ball Grid Arrays (BGAs) or Chip Scale Packages (CSPs) during the rework process.
Knocking Down the Bone Pile: Basics of Component Lead Tinning
04/02/2025 | Nash Bell -- Column: Knocking Down the Bone PileThe component lead tinning process serves several critical functions, including removing gold plating, mitigation of tin whiskers, reconditioning of component solderability issues, and alloy conversion from lead-free (Pb-free) to tin-lead or from tin-lead to lead-free for RoHS compliance. We will cover each of these topics in more detail in upcoming columns.
Real Time with... IPC APEX EXPO 2025: MKS' Atotech—Leading Innovations in Semiconductor Solutions
03/28/2025 | Real Time with...IPC APEX EXPOIn this interview, Marcy LaRont speaks with Kuldip Johal, CTO, MKS’ Atotech. Based in Boston, MKS operates in vacuum solutions, photonics, and specifically for the Atotech division, material solutions. MKS significantly impacts the semiconductor industry, supplying components for up to 85% of global semiconductor tools and covers processes and materials for 70% of PCB manufacturing steps.
KYZEN to Highlight Stencil and Cleaning Solutions at SMTA Monterrey
03/27/2025 | KYZEN'KYZEN, the global leader in innovative environmentally friendly cleaning chemistries, will exhibit at the SMTA Monterrey Expo & Tech Forum scheduled to take place on Thursday, April 10 at the Cintermex Convention Center in Monterrey, Nuevo León. KYZEN cleaning experts will be on-site highlighting stencil cleaning chemistries KYZEN E5631J and CYBERSOLV C8882.
HARTING 3D-Circuits Leads 3D-MID Innovation: Transforming Consumer Electronics with Advanced Technology
03/27/2025 | PRNewswireThe consumer electronics industry is experiencing a remarkable transformation, propelled by rapid technological advancements and an increasing demand for compact, efficient, and multifunctional devices. Central to this evolution is 3D-MID (Three-Dimensional Mechatronic Integrated Devices) technology, which redefines design standards and drives innovation.