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Trouble in Your Tank: Technology Trends and Direct Metallization
In the recent IPC 2018 Technology Trends report, there are several very important trends that bare board fabricators should be aware of and plan for accordingly. These trends are moving quite fast, and for some, investment in equipment as well as adapting to new materials and processes will be needed.
High-density Interconnect (HDI)
HDI is not new as far as the trends go; however, HDI is now mainstream technology. Today, HDI is the fastest-growing segment of interconnect packaging used in portable products, IC, and ASIC packaging and large, complex multilayers for telecom and servers.
HDI provides the following:
- Reduction in layer count for thickness control and RoHS compliance (lead-free assembly)
- Method to integrate high-I/O and fine-pitch devices without adding layers
- Method to achieve higher component density and component I/Os without adding more layers
The use of blind vias provides opportunities to increase routing. As one can easily imagine, HDI is more than just miniaturization; it is an opportunity to adapt a technology to enable complex designs without compromising reliability and cost.
Let’s properly frame the situation related to HDI and the current and future (projected) landscape. IPC recently published the results 2018 Technology Trends survey. A key finding of the survey showed that the majority of the OEMs surveyed anticipate that they will require blind vias on two or more layers by 2023. In addition, a high percentage of the participating OEMs specify buried vias today, and more expect to do so by 2023[1].
As Happy Holden has pointed out in one of his many articles, designs with both multilayer blind vias and buried vias allow designers to reduce layer counts while increasing wiring density[2]. Originally, the board shown in Figure 1 was a 26-layer through-hole-only board. By redesigning the structure to meet design rules and satisfy routing density, the 26-layer board was reduced to the design shown in Figure 1. This is significant both from the stand-point of cost reduction and routing density.
Of course, such a drastic change in design spurs changes as well as opportunities in processes. One such opportunity arises with the use of direct metalization as an alternative to conventional electroless copper.
Graphite-based Direct Metallization
Colloidal graphite direct metallization processes have proven their usefulness as a re-placement for electroless copper. This is especially the case in high technology and quick-turn applications. The ability of the colloidal graphite to successfully enable the direct electroplating of difficult-to-metalize materials—such as polyimide, PTFE, ceramic-filled resins, PPO, and PPE—is well documented.
Aiding this has been the improvement of the consistency of colloidal graphite direct metallization processes. This is accomplished through a better understanding of the influence of conditioning agents, the stability of the dispersion, and other process refinements that will be detailed in this column. The implementation of polyelectrolyte surface-active agents that enhance the adsorption of the graphite to the non-conductive surfaces without causing excessive film thickness is quite critical. And the introduction of post-process technology further enhances the uniformity and conductivity of the graphite coating. These improvements are necessary as the industry migrates to more complex designs.
The key takeaway here is quite simple: Direct metallization is an ideal process for HDI applications.
Application of Graphite Metallization for Flexible Circuits and HDI
While graphite-based direct metallization is a production-proven process for rigid PCBs, the process is also gaining a much larger share of the new capacity coming on line for HDI and flexible circuits. A major driver is the higher cost of equipment for electroless copper versus direct metallization. In addition, as has been described elsewhere in this column, the productivity of a graphite-based direct metallization process is much greater than conventional electroless copper. Most important, though, is the inherent ability of the graphite system to readily adhere to a wide variety of laminate substrates and materials, including polyimide, PTFE, ceramic filled materials, PPO, PPE, halogen-free, and many other materials. As laminate suppliers continue to reinvent themselves to stake out a position in higher technology, a versatile metallization process is critical to success.
So, why be concerned with the different laminate materials? Aside from the obvious, successful metallization requires that excel-lent adhesion between the conductive coating (either electroless copper or conductive graphite) be achieved. It is well-documented that adhesion is favored when there is sufficient surface topography to promote the bond. This is especially true for electroless copper as the seeding of the palladium is required to initiate the copper deposition. However, as one views the SEM in Figure 2, the topography visible after permanganate desmear is rather smooth and unremarkable, further impacting the adhesion factor.
A critical advantage for the graphite-based system is that the colloidal graphite binds to resin and glass without the need for a high surface area. It is important to recognize that electroless copper is a plating process, where-by a series of reactions take place in order to effect a deposit. In the case of the graphite-based metallization system presented herein, the mechanism is primarily a coating process whereby the binder technology acts to pro-mote adhesion of the graphite particles to even the smoothest of surfaces. Electroless copper lacks in this area.
Fabricators must embrace changes in the way printed wiring boards are processed. Direct metallization based on colloidal graphite is an enabling technology for HDI designs and flexible circuits. Stay tuned for future columns on direct metallization.
References
1. IPC, “IPC 2018 Technology Trends Survey,” and “IPC APEX EXPO 2019 Buzz Session.”
2. Holden, H., “How to Get Started in HDI With Microvias,” CircuiTree (online article), November 2003.
This column originally appeared in the January 2020 issue of PCB007 Magazine.
More Columns from Trouble in Your Tank
Trouble in Your Tank: Interconnect Defect—The Three Degrees of SeparationTrouble in Your Tank: Things You Can Do for Better Wet Process Control
Trouble in Your Tank: Processes to Support IC Substrates and Advanced Packaging, Part 5
Trouble in Your Tank: Materials for PWB Fabrication—Drillability and Metallization
Trouble in Your Tank: Supporting IC Substrates and Advanced Packaging, Part 5
Trouble in Your Tank: Electrodeposition of Copper, Part 6
Trouble in Your Tank: Electrolytic Copper Plating, Part 5
Trouble in Your Tank: Processes to Support IC Substrates and Advanced Packaging, Part 4