-
- News
- Books
Featured Books
- pcb007 Magazine
Latest Issues
Current IssueInner Layer Precision & Yields
In this issue, we examine the critical nature of building precisions into your inner layers and assessing their pass/fail status as early as possible. Whether it’s using automation to cut down on handling issues, identifying defects earlier, or replacing an old line...
Engineering Economics
The real cost to manufacture a PCB encompasses everything that goes into making the product: the materials and other value-added supplies, machine and personnel costs, and most importantly, your quality. A hard look at real costs seems wholly appropriate.
Alternate Metallization Processes
Traditional electroless copper and electroless copper immersion gold have been primary PCB plating methods for decades. But alternative plating metals and processes have been introduced over the past few years as miniaturization and advanced packaging continue to develop.
- Articles
- Columns
Search Console
- Links
- Media kit
||| MENU - pcb007 Magazine
Estimated reading time: 3 minutes
Contact Columnist Form
Trouble in Your Tank: Lamination and Delamination
There are many reasons to get incredibly frustrated and confused when presented with complex issues related to the PCB fabrication process. There is much room for error, and often, the simplest little detail overlooked leads to significant product quality loss. Consider the design requirements, along with more stringent reliability performance, and there is a recipe for defects, such as delamination. Let’s review the concerns with the possibility of multilayer board delamination and the root cause or causes of the defect.
Delamination Versus Laminate Voids
When reviewing the potential root cause of delamination, the first thing the troubleshooter must do is determine if the anomaly is delamination or a lamination void. They are different as to the root causes of each. And once this is recognized, the protocol—along with fishbone diagrams and brainstorming—can begin. Voids are not a separation of the resin from the copper. Rather voids are basically air pockets formed within the multilayer package. An example of laminate voids is shown in Figure 1.
IPC-T-50 de?nes a void in laminate as a circular pocket within resinous area of laminate, usually formed by entrapped air or volatile materials and at or near the surface of the laminate.
The prepreg or prepreg/laminate surface may show small voids. These may expand when subjected to soldering or re?ow. Small voids in the board may bridge conductors, pick up moisture, and cause electrical shorts.
Delamination is a horse of a different color. Delamination is defined by IPC T-50 as “a separation between plies within a base material, between a base material and a conductive foil, or any other planar separation within a printed board”—the key concept being separation.
Blisters, even on inner layers, affect the surface of the printed board. A bubble will be able to be felt when touched. Understanding the root cause, however, is most critical at this juncture. A blister doesn’t necessarily equate to classic delamination. Nonetheless, the blister is a separation and most likely caused by moisture within the laminate package. What is critical to understand is whether there is a separation from the copper surfaces where the resin is separated (Figure 2).
The microsection in Figure 2 is a good depiction of classic delamination. There are a number of factors that can contribute to the delamination shown in Figure 2. Table 1 provides a good overview of the causes of delamination.
As the reader can surmise, there are many variables to monitor and check if the process is not in proper control. However, delamination also occurs within the resin itself for a number of reasons (Figure 3).
Since this is not classic delamination, what is the probable cause here? One probable cause is moisture remaining in the laminate material. One cannot assign the cause of this defect to the inner layer preparation process as there is no separation of the resin from the copper surface, as shown in Figure 2. For the issue noted in Figure 3, a thorough review of the prepreg storage conditions—as well as the lamination cycle—is in order. If a single-stage press cycle was used in this case, one should switch to a dual-stage lamination cycle. While up to 10–12-layer multilayer boards are amenable in a single stage, in most board stackups, the dual-stage or kiss cycle has advantages for higher layer counts as well. The release of volatiles is optimized during the low-pressure portion of the kiss cycle.
Another probable cause of delamination within the resin itself is defective incoming material from the supplier. If the fabricator has taken all necessary precautions to ensure proper storage of the prepreg, including storage at low humidity and low temperature, this issue requires a new lot of prepreg material.
Remember, the printed wiring board fabrication process is made of chemical and mechanical processes. Understand how these work together to ensure the fabrication of a high-quality product.
This column originally appeared in the May 2020 issue of PCB007 Magazine.
More Columns from Trouble in Your Tank
Trouble in Your Tank: Interconnect Defect—The Three Degrees of SeparationTrouble in Your Tank: Things You Can Do for Better Wet Process Control
Trouble in Your Tank: Processes to Support IC Substrates and Advanced Packaging, Part 5
Trouble in Your Tank: Materials for PWB Fabrication—Drillability and Metallization
Trouble in Your Tank: Supporting IC Substrates and Advanced Packaging, Part 5
Trouble in Your Tank: Electrodeposition of Copper, Part 6
Trouble in Your Tank: Electrolytic Copper Plating, Part 5
Trouble in Your Tank: Processes to Support IC Substrates and Advanced Packaging, Part 4