Andes Announces New RISC-V Processors

Estimated reading time: 2 minutes

Andes Technology Corporation, the leader in RISC-V CPU solutions, today proudly announces new members of AndesCore™: high performance superscalar A45MP and AX45MP multicore processors, and A27L2 and AX27L2 processors with Level-2 (L2) cache controller.

The AndesCore™ 45-series IPs are in-order 8-stage dual-issue RISC-V processors, and equipped with optional DSP (RISC-V P-extension) unit, single or double precision Floating Point Unit and MMU (Memory Management Unit) that supports Linux-based applications as well. Its performance-efficient single core members, including 32-bit A45/D45/N45 and 64-bit AX45/NX45, have already been designed in by several customers since they are available last quarter. The new multi-core members, 32-bit A45MP and 64-bit AX45MP, support up to 4 cores with an optional L2 cache controller to meet the computing demands of heavy-duty applications such as AR/VR, AI/machine learning, 5G, In-Vehicle Infotainment (IVI), Advanced Driver Assistance Systems (ADAS), video/image processing, enterprise-grade storage device, and networking.

The newest members of the AndesCore™ 27-series, 32-bit A27L2 and 64-bit AX27L2, inherit the MemBoost feature, first made available in the 27-series, where multiple outstanding data accesses and I/D cache prefetch greatly boost the memory subsystem performance with higher bandwidth and lower access latencies. To bring the performance of memory-intensive applications to the next level, the L2 cache controller of the A27L2 and AX27L2 further raise memory bandwidth by 2x and reduce memory latencies by 70%.

“45MP processors are very important landmarks for Andes and RISC-V enthusiasts,” said Andes President, Frankwell Lin. “Our customers are looking to replace their high-performance application processors. It is exciting to see Andes RISC-V multi-core processors perfectly meet their expectations. Its directory-based coherence protocol allows the 45-series processors to support a larger multicore. In the meantime, we are happy to announce the availability of new members of 27-series, A27L2 and AX27L2. These two new cores provide an integrated L2 cache controller which makes them excellent for entry-level Linux-based applications requiring for the most power-efficient processor.”

“Multicore processors boost performance by using more cores and are suitable for applications with high parallelism. The 45MP supports up to four CPU cores with a Coherence Manager and an optional L2 cache controller. The Coherence Manager ensures cache coherence between Level-1 (L1) caches, the L2 cache, and cacheless bus masters, and help deliver efficient transactions for shared memory accesses,” said Dr. Charlie Su, CTO and Executive VP of Andes. “Compared with the single-issue 27-series processors, the well-designed dual-issue 45-series processors achieve more than 70% total performance enhancement with less than 50% additional logic area and dynamic power consumption. Furthermore, their maximum operating frequency can run up to 2.4 GHz at the popular 12nm process node,” Dr. Charlie Su further explained. “Similarly, the 27L2 processors with L2 cache controller and MemBoost are perfect for those designs that need only single core, but still require substantial performance on memory subsystem. The 45-series and 27-series together provide a wide spectrum of processor solutions to address diversified SoC requirements.”

All the new cores fully support Andes V5 architecture. Therefore, they are compliant with the most updated RISC-V extensions, and also all Andes V5 novel features such as PowerBrake, QuickNap™, and WFI for additional power saving; StackSafe™ for stack overflow/underflow protection; and CoDense™ for additional code density enhancement on top of RISC-V C-extension. Furthermore, the 45-series and 27-series processors benefit from all Andes development tools such as AndeSight™ IDE and Andes Custom Extension™ framework as well as RISC-V ecosystem from security solutions to system level modeling, and hardware debug/trace subsystems.