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Verific, DARPA Partner to Streamline Access to SystemVerilog EDA Software
December 18, 2020 | Globe NewswireEstimated reading time: 1 minute
Verific Design Automation has announced a partnership agreement with the U.S. Defense Advanced Research Projects Agency (DARPA) to provide the DARPA community access to its electronic design automation (EDA) software in production and development use throughout the semiconductor industry.
Driven by the DARPA Electronics Resurgence Initiative (ERI) to forge collaborations among commercial electronics companies, the agreement offers the DARPA community use of Verific’s hardware description language (HDL) software for the duration of their programs.
“Our support of academic use over the years has been on an ad-hoc basis,” remarks Michiel Ligthart, president and chief operating officer of Verific. “This agreement provides DARPA-funded programs easy and streamlined access to our industry-standard SystemVerilog parsers and elaborators, cracking open ways to meet DARPA’s goal to innovate a fourth wave of electronics progress.”
Specific tools covered under the agreement are Verific's SystemVerilog parser and static and register transfer logic (RTL) elaborators, already serving as front-end for simulation, formal verification, synthesis, emulation, virtual prototyping, in-circuit debug and design for test applications worldwide. For years, Verific's Parser Platforms have given engineering groups a way to eliminate costly internal development of front-end EDA software, accelerating time to market with improved quality.
Currently, more than 20 DARPA-funded programs promote U.S. microelectronics leadership, including some using low-cost, predictably priced tools such as Verific’s software. “DARPA’s programs within the Microsystems Technology Office (MTO) are a bold accelerator of several technical and economic trends in the microelectronics sector,” says Serge Leef, who leads design automation and secure hardware programs. “Giving DARPA’s community easy access to proven, industrial-strength, best-in-class software frameworks enables the researchers to tightly focus on scientific advances while improving the path to a smooth transition of their breakthrough discoveries into commercial and defense applications.”
Verific’s SystemVerilog, VHDL and universal power format (UPF) Parser Platforms are in production and development flows at semiconductor companies worldwide, from emerging companies to established Fortune 500 vendors. Verific distributes its Parser Platforms as C++ source code and compiles on all 32- and 64-bit Unix, Linux, Mac OS and Windows operating systems.
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