New iNEMI Project on High Density Interconnect Socket Warpage Prediction
December 14, 2022 | iNEMIEstimated reading time: 1 minute

High density interconnect sockets are becoming larger, which creates challenges for socket warpage simulation and can impact SMT assembly yield and reliability. Expedited computation that maintains the required level of accuracy is needed to shorten socket design cycles.
Phase 1 of iNEMI’s High Density Interconnect Socket Warpage Prediction and Characterization project established an analysis and validation framework for socket development, conducted simulation experiments, and initially investigated the impact of socket design, fiber filled material properties and molding process conditions on socket warpage.
Phase 2 will focus on improving socket warpage simulation accuracy and speed, further investigating the impact of molding and design on socket warpage, and will ultimately establish guidelines for dynamic socket warpage measurement and prediction. If you are involved in socket design and development, board assembly and/or reliability, this project will be of interest to you. Please join us to learn more on January 5 or 6. The deadline to sign up for the project is February 17, 2023.
Registration
This webinar is open to industry; advance registration is required.
Session 1
Thursday, January 5, 2023
7:00-8:00 a.m. EST (U.S.)
1:00-2:00 p.m. CET (Europe)
8:00-9:00 p.m. CST (China)
Session 2
Friday, January 6
9:00-10:00 a.m. CST (China)
8:00-9:00 p.m. EST (U.S.) on January 5
Suggested Items
Bridging the Gap Between PCB Designers and Fabricators
04/03/2025 | Stephen V. Chavez, Siemens EDAWith today’s advanced EDA tools, designing complex PCBs in the virtual world does not necessarily mean they can be built in the real world. This makes the relationship between a PCB designer and a fabricator pivotal to the success of a project. In keeping with solid design for manufacturing (DFM) practices, clear and frequent communication is needed to dial and lock in design constraints that meet expectations while addressing manufacturing concerns.
IPC APEX EXPO Newcomer: Faith DeSaulnier of TTM Technologies
04/03/2025 | I-Connect007 Editorial TeamDuring the Newcomer’s Welcome Reception at IPC APEX EXPO, the I-Connect Editorial Team spoke with several first-time attendees. The following is our interview with Faith DeSaulnier, a process engineer based at TTM Technologies’ facility in Forest Grove, Oregon.
Ansys Semiconductor Solutions Certified by TSMC for Reliable, Accurate Analysis of Evolving Chip Designs
04/03/2025 | PRNewswireAnsys announced that PathFinder-SC is certified as a new ESD analysis solution for customers designing with TSMC's N2 silicon process technology. PathFinder-SC delivers a novel verification solution that provides superior capacity and performance, easily accommodating large designs in the cloud.
Real Time with... IPC APEX EXPO 2025: Insights into PCB Design and Manufacturing with Polar Instruments
04/03/2025 | Real Time with...IPC APEX EXPOErik Bateham discusses Polar's latest book, which enhances insights for PCB designers and manufacturers. The book, "The Designer's Guide to... More Secrets of High-Speed PCBs," features a guest chapter on 2D via design modeling. Erik highlights the industry's shift towards UHDI and the challenges in measuring at micron levels.
Connect the Dots: Stop Killing Your Yield—The Hidden Cost of Design Oversights
04/03/2025 | Matt Stevenson -- Column: Connect the DotsI’ve been in this industry long enough to recognize red flags in PCB designs. When designers send over PCBs that look great on the computer screen but have hidden flaws, it can lead to manufacturing problems. I have seen this happen too often: manufacturing delays, yield losses, and designers asking, “Why didn’t anyone tell me sooner?” Here’s the thing: Minor design improvements can greatly impact manufacturing yield, and design oversights can lead to expensive bottlenecks. Here’s how to find the hidden flaws in a design and avoid disaster.