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January 23, 2023 | AveratekEstimated reading time: 1 minute
Averatek is pleased to announce that Director of Advanced Process Development Gus Karavakis will present “Thermal Stress Reliability of Stacked Microvias Fabricated with a Liquid Metal Ink Semi-Additive Process” at the IPC APEX Expo Technical Conference, January 24-26, 2023 in the San Diego Convention Center. The technical paper was co-authored by Mike Carano, IPC Technology Roadmap Committee Chair and member of the Board of Directors.
The drive to miniaturization makes the smaller footprint of stacked vias more desirable in terms of routing and design efficiency than staggered vias. However, there is evidence that stacked vias are prone to latent failures after exposure to thermal stress of conventional surface mount technology (SMT) reflow processes. This issue is broadly defined as a weak interface between the plated copper and the blind via target pad. When thermally stressed, the generally weak interface will fracture, especially during forced-convection assembly reflow.
While many studies of microvia interfacial fracture focused on conventional electroless copper as the plated through-hole (PTH) choice, no recent studies measured the reliability of stacked microvias with a semi-additive process (SAP) using a liquid metal ink as the catalytic layer.
This novel catalytic ink promotes a tightly adherent and ultrathin electroless copper deposit. The lower thickness enables much finer line spaces and trace widths than conventional subtractive-etch or modified semi-additive processes (mSAP). Liquid metal ink technology enables capability for 5micron lines and spaces; the tighter line width control will benefit the impedance control.
To measure reliability of the liquid metal ink process, test vehicles were constructed and subjected to Thermal Shock and Thermal Stress testing, according to protocols in IPC-TM-650 Test Method 2.6.27B. Complete results of this study will be covered in the presentation.
Test results indicate that the liquid metal ink process provides long-term reliability on two-stack blind vias, while offering distinct functionality advantages beyond conventional subtractive and mSAP processes.
Gus Karavakis has over 30 years of industry experience, with special expertise in advanced processes, additive technologies, IC Packaging and substrates, flex and rigid-flex PCB manufacturing and materials. He is the author/co-author of more than 80 patents, and holds a BE in Chemical Engineering from CCNY with an MS in Chemical Engineering from Columbia University.
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