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The Impact of Chip Packaging
February 1, 2023 | Charles E. Bauer, Ph.D., TechLead CorporationEstimated reading time: 1 minute
When talking about chip packaging impacts on substrates and electronic manufacturing services (EMS) providers, the focus mostly lies on large packages and very high I/O, fine pitch components; rightly so in most cases. However, several current packaging trends offer a new path forward to simplification and, thereby, cost reduction in both the printed wiring board (PWB) and EMS supply chains.
A handful of key technologies support these advances. Through silicon vias (TSV), while tracing their origins back to the invention of the transistor and found in a few supercomputers during the 1980s, really came onto the volume manufacturing scene between 2005 and 2010. Since that time, rapid advances in process control and yield led to very high-density memory implementations. TSV now proves a key enabler in the evolution of chiplet architectures.
The second key technology development came in the form of silicon and glass substrate development. Silicon substrates entered the scene in a significant manner during the 1990s but, until recently, proved too expensive for all but the most esoteric applications. The availability of old node fabrication equipment that flooded the market around 2008–10, opened the door to more reasonably priced Si substrate and provided an easy path to the current chiplet architecture, particularly for large IC OEMs. The advent of glass substrates, driven by extensive research at the Georgia Tech Packaging Research Center, now provides very high routing capability comparable with silicon substrates at far lower cost. The compatibility between the coefficient of thermal expansion (CTE) of glass and Si chips makes for highly reliable, multichip assembly either in a chiplet or SiP application.
To read this entire article, which appeared in the January 2023 issue of PCB007 Magazine, click here.
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