UMC, Cadence Collaborate on 3D-IC Hybrid Bonding Reference Flow
February 7, 2023 | Cadence Design Systems, Inc.Estimated reading time: 1 minute
United Microelectronics Corporation, a leading global semiconductor foundry, and Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the Cadence® 3D-IC reference flow, featuring the Integrity™ 3D-IC Platform, has been certified for UMC’s chip stacking technologies, enabling faster time to market.
UMC’s hybrid bonding solutions are now ready to support the integration across a broad range of technology nodes that are suitable for edge AI, image processing, and wireless communication applications. Using UMC’s 40nm low power (40LP) process as a wafer-on-wafer stacking demonstration, the two companies collaborated to validate key 3D-IC features in this design flow, including system planning and intelligent bump creation with Cadence’s Integrity 3D-IC platform, the industry’s first comprehensive solution that integrates system planning, chip and packaging implementation, and system analysis in a single platform.
“Interest in 3D-IC solutions has increased notably in the past year as our customers seek ways to boost design performance without sacrificing area or cost,” said Osbert Cheng, vice president of device technology development & design support at UMC. “Cost-effectiveness and design reliability are the pillars of UMC’s hybrid bonding technologies, and this collaboration with Cadence provides mutual customers with both, helping them reap the benefits of 3D structures while also accelerating the time needed to complete their integrated designs.”
"With increasing design complexity for IoT, AI, and 5G applications, wafer-on-wafer technology automation is increasingly important for chip designers,” said Don Chan, vice president, R&D in the Digital & Signoff Group at Cadence. “The Cadence 3D-IC flow with the Integrity 3D-IC platform is optimized for use on UMC’s hybrid bonding technologies, providing customers with a comprehensive design, verification and implementation solution that enables them to create and verify innovative 3D-IC designs with confidence while accelerating time to market.”
The reference flow, featuring Cadence’s Integrity 3D-IC Platform, is built around a high-capacity, multi-technology hierarchical database. The platform offers design planning, implementation and analysis of full 3D designs within a single, unified cockpit. Multiple chiplets in a 3D stack can be designed and analyzed together through integrated early analysis for thermal, power and static timing analysis. The reference flow also enables system-level layout versus schematic (LVS) checking to connectivity accuracy, electric rule-checking (ERC) for coverage and alignment checking, and thermal analysis for heat distribution in a 3D stacked-die design structure.
Suggested Items
Micross, Sital Announce Global Manufacturing & Distribution Partnership
05/07/2024 | Micross Components, Inc.Micross Components, Inc., a leading global provider of mission-critical microelectronic components and services for high-reliability aerospace, defense, space and industrial applications, is pleased to announce our exclusive partnership with Sital Technology (sitaltech.com), the leader in MIL-STD-1553 IP cores, specializing in integrated FPGA solutions.
Real Time with… IPC APEX EXPO 2024: Innovative Lamination Technology
05/07/2024 | Real Time with...IPC APEX EXPOKevin Barrett of Insulectro and Victor Lazaro of Indubond discuss their companies' partnership, focusing on Indubond's innovative lamination technology that uses induction heating. They discuss the advantages of this technology over traditional methods, its benefits to customers, and the crucial role of automation in manufacturing.
Indium Corporation to Showcase HIA Materials at ECTC
05/07/2024 | Indium CorporationAs an industry leader in innovative materials solutions for semiconductor packaging and assembly, Indium Corporation® will feature its advanced products designed to meet the evolving challenges of heterogeneous integration and assembly (HIA) and fine-pitch system-in-package (SiP) applications at the 74th Electronic Components and Technology Conference (ECTC), May 28‒31, in Denver, Colorado.
IDTechEx Discusses Low-Loss Materials: The Enabler of Future Connected Vehicles?
05/06/2024 | IDTechExFuture connected vehicles will offer future drivers a safer, smoother, and more convenient driving experience. Not only will drivers get access to more navigation and entertainment options, but they will also gain access to safety technologies that will potentially reduce accidents, improve congestion, and reduce emissions globally by allowing vehicle safety systems to communicate with each other and with city traffic infrastructure.
BrainChip, Frontgrade Gaisler to Augment Space-Grade Microprocessors with AI Capabilities
05/06/2024 | BUSINESS WIREBrainChip Holdings Ltd, the world’s first commercial producer of ultra-low power, fully digital, event-based, neuromorphic AI IP, and Frontgrade Gaisler, a leading provider of space-grade system-on-chip solutions, announce their collaboration to explore the integration of BrainChip’s AkidaTM neuromorphic processor into Frontgrade Gaisler’s next generation fault-tolerant, radiation-hardened microprocessors.