The Chemical Connection: Getting the Best from Your Cupric Chloride Etchant
It’s Only Common Sense: The Dangers of Staying Stagnant in a Changing World
Dan’s Biz Bookshelf: ‘Born to Create’
StratEdge Reveals High-Performance Semiconductor Packages at European Microwave Week, IMAPS International, and IEEE BCICTS
September 19, 2023 | StratEdgeEstimated reading time: Less than a minute
StratEdge Corporation will present its thermally-efficient line of post-fired and molded ceramic semiconductor packages at several upcoming events including European Microwave Week (EuMW), September 19-21, IMAPS International, October 3-4, and IEEE BCICTS, October 16-17. StratEdge packages dissipate heat from compound semiconductor devices such as gallium nitride (GaN), gallium arsenide (GaAs), and silicon carbide (SiC) and operate from DC to 63+ GHz. The packages provide ultra-low loss performance over a wide range of frequencies, depending on the style and mounting configuration. Many open-tooled designs are available with 50 ohm impedance, which provide convenience and ease for packaging your high-performance semiconductors.
Casey Krawiec, VP of Global Sales at StratEdge, emphasized, "We manufacture our packages with precision, using post-fired ceramics with laser-cut features to control tight tolerances, thermally-enhanced metal bases that dissipate heat, and electrical transition designs that provide exceptionally low electrical losses. For further optimized performance, StratEdge Assembly Services can package your devices in our new cleanroom, equipped with the latest precision wire bonding and die attach systems."
Share on:
Suggested Items
ZESTRON South Asia releases whitepaper – Impact of Cleaning Technology on Discrete Packaging - The Difference in Wire Bonding Yield
12/02/2024 | ZESTRONZESTRON, the global leading provider of high precision cleaning products, services, and training solutions in the electronics manufacturing and semiconductor industries, is pleased to release the whitepaper “Impact of Cleaning Technology on Discrete Packaging - The Difference in Wire Bonding Yield”
Würth Elektronik Expands Signal LED Product Range
11/21/2024 | Wurth ElectronicsWürth Elektronik expands its proven LED product series WL-SMCW and WL-SMCC with white LEDs in 0603 and 0402 packages.
Unlock Unmatched Performance for Matched Impedance Devices with StratEdge at IEEE BCICTS 2024
10/22/2024 | StratEdgeStratEdge Corporation, an industry leader in high-frequency and high-power semiconductor packaging, is excited to announce its participation in the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS).
TopLine to Exhibit 'Drop-in Replacement' for BGA at Electronica
10/16/2024 | TopLineTopLine Corporation will exhibit its latest technology solutions at Electronica in Munich, Germany, November 12 – 15, 2024, in stand B4.428.
PCB Surface Topography and Copper Balancing Under Large Form Factor BGAs
10/01/2024 | Neil Hubble, Akrometrix and Gary A. Brist, Intel CorporationAs CPU and GPU packages grow larger and contain higher pin/ball counts, the importance of managing the printed circuit board (PCB) surface coplanarity for package assembly increases. The PCB surface coplanarity under a package is a product of both the global bow/twist of the PCB and the local surface topography under the package. In general, the surface topography is dependent the choice of material and layer stackup and the interaction between the innerlayer copper patterns and prepreg resin flow.