StratEdge Reveals High-Performance Semiconductor Packages at European Microwave Week, IMAPS International, and IEEE BCICTSSeptember 19, 2023 | StratEdge
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StratEdge Corporation will present its thermally-efficient line of post-fired and molded ceramic semiconductor packages at several upcoming events including European Microwave Week (EuMW), September 19-21, IMAPS International, October 3-4, and IEEE BCICTS, October 16-17. StratEdge packages dissipate heat from compound semiconductor devices such as gallium nitride (GaN), gallium arsenide (GaAs), and silicon carbide (SiC) and operate from DC to 63+ GHz. The packages provide ultra-low loss performance over a wide range of frequencies, depending on the style and mounting configuration. Many open-tooled designs are available with 50 ohm impedance, which provide convenience and ease for packaging your high-performance semiconductors.
Casey Krawiec, VP of Global Sales at StratEdge, emphasized, "We manufacture our packages with precision, using post-fired ceramics with laser-cut features to control tight tolerances, thermally-enhanced metal bases that dissipate heat, and electrical transition designs that provide exceptionally low electrical losses. For further optimized performance, StratEdge Assembly Services can package your devices in our new cleanroom, equipped with the latest precision wire bonding and die attach systems."
Martin Hart, CEO of TopLine Corporation, will deliver a presentation titled “Reliable Solder Columns to Replace Solder Balls in Large 2.5D Heterogeneous Packages” at IMAPS 2023 in San Diego, California, October 4, 2023.
Martin Hart, CEO of TopLine Corporation, will deliver a presentation titled “Next Generation Solder Columns Extend Life for Large Packages for Space Applications and Data Centers” at the upcoming 14th Annual NASA Electronic Parts and Packaging (NEPP) Electronics Technology Workshop (ETW) June 13.
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ViTrox, which aims to be the world’s most trusted technology company, is excited to announce the launch of the enhanced Tray-based Vision Handler, TR1000S?i!
Over seven years ago, I put pen to paper to enumerate the top challenges needing to be overcome for a successful BGA rework. With the continued advancement of BGA technology, it’s time to apply a fresh coat of paint to that list. Read on to find out my revised take on today’s top BGA rework challenges. As devices become more complex and computing power requirements increase, the maximum physical size of BGA packages has increased as well. Currently, some devices in development are planned to be 125 mm x 125 mm in size. These large package sizes present some very challenging scenarios for rework process technicians.