IPC, FED Partner for New Design Conference in Vienna
December 12, 2024 | Andy Shaughnessy, Design007 MagazineEstimated reading time: 2 minutes

IPC and its German partner FED have teamed up to create a new PCB design conference in Vienna, Austria. The Pan-European Electronics Design Conference (PEDC) is scheduled for Jan. 29-30 at the NH Danube City hotel in Vienna.
IPC’s Peter Tranitz, one of the show organizers, discussed how this new show came about, pointing out that, unlike many of the regional conferences in Europe, PEDC will host curated, peer-reviewed presentations, not promotional content or product pitches. Will PEDC become an annual event?
Andy Shaughnessy: Peter, tell us about the new design conference in Vienna, Austria.
Peter Tranitz: The idea for the Pan-European Electronics Design Conference came out of discussions that IPC and FED (Germany-based electronics design and manufacturing association) had with the PCB and EMS communities around our activities in Brussels. During those discussions, we learned that high-level scientific conferences are missing within the European landscape. In Europe, we have regional language conferences on electronic design organized by national associations. Often, little care is taken to avoid promotional and product pitches.
The PEDC is targeting the pan-European community for electronics design. We are transporting the model of the IPC APEX EXPO conference, which excludes commercialism and ensures a high level of technical content for the presentations. Our technical program committee is targeting content with a high technical and scientific level. This pure, technically scientific approach is the differentiator from other events happening in Europe. We prefer presentations that haven't been published before, so that attendees see the content for the first time.
Shaughnessy: Are the presentations in English? What does the program consist of?
Tranitz: Yes, it’s all English. We are open to engineers of all levels to academia and students, and we embrace diversity. We are seeking European participants as well as interested people from around the globe. Our Day 1 program consists of two keynotes. One is focused on electronic design and AI utilization, and the other keynote is around silicon-to-systems development. We have two panels: One tackles AI in electronics, and the other focuses on regulations and sustainability. These are big topics, especially in Europe.
On Day 2, we have two tracks with 12 presentations, each in parallel. One track focuses on silicon-to-systems and design techniques, and the other is around design for excellence, software, and tools. We’ve managed to engage professors from academia, top experts from research institutes, and companies that do a lot of research and development to help us set up a very attractive program. It is also worth mentioning that we have received far more presentation abstracts than we can cover at the conference.
To read this entire conversation, which appeared in the December 2024 issue of Design007 Magazine, click here.
Suggested Items
Würth Elektronik Now an Infineon ‘Preferred Partner’
03/13/2025 | Wurth Elektronik eiSosWürth Elektronik, one of the leading manufacturers of electronic and electromechanical components, is broadening its collaboration with semiconductor manufacturers.
Elementary Mr. Watson: Ensuring a Smooth Handoff From PCB Design to Fabrication
03/13/2025 | John Watson -- Column: Elementary, Mr. WatsonAt the 2020 Tokyo Summer Olympics, the U.S. men's 4x100-meter relay team had high hopes of winning a medal. The team comprised some of the fastest sprinters in the world, but something went wrong. In a relay, four runners must smoothly pass their baton to the next runner inside a zone on the track. If a runner drops the baton or it’s passed outside the zone, the team risks disqualification. The U.S. team’s pass between the second and third runner was messy, slowing them down. By the time the last runner received the baton, the team had lost too much time. They finished sixth in their heat and didn’t qualify for the final.
Ventec International Group Announce Launch of VT-47LT IPC4101 /126 Prepreg for HDI
03/12/2025 | Ventec International GroupVentec International Group announce launch of VT-47LT IPC4101 / 126 Prepreg. Are Microvia Failures Plaguing Your HDI Any Layer Designs? High-density interconnect (HDI) designs are pushing the envelope - higher layer count HDI relies on complex microvia designs: skip vias, staggered microvias, and stacked microvias in sequential laminations.
TI Introduces the World's Smallest MCU, Enabling Innovation in the Tiniest of Applications
03/12/2025 | PRNewswireTexas Instruments (TI) introduced the world's smallest MCU, expanding its comprehensive Arm® Cortex®-M0+ MSPM0 MCU portfolio. Measuring only 1.38mm2, about the size of a black pepper flake, the wafer chip-scale package (WCSP) for the MSPM0C1104 MCU enables designers to optimize board space in applications such as medical wearables and personal electronics, without compromising performance.
Speaking the Same Language as Your Fabricator
03/12/2025 | Andy Shaughnessy, Design007 MagazineWe do indeed have a failure to communicate; designers and fabricators often seem to be talking past each other, which can lead to jobs being put on hold. We asked Jen Kolar, VP of engineering for Monsoon Solutions, and columnist Kelly Dack to share their thoughts on ways that we can break down the communication barrier between design and fabrication. As they point out, a design kickoff checklist and a solid review process can be invaluable tools in a designer’s toolbox.