Advanced Packaging-to-Board-Level Integration: Needs and Challenges

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A White Paper from Global Electronics Association Technology Solutions Group

Application Needs for Component-Level Packaging & System-Level Packaging

High-Performance Computing (HPC)
HPC data center markets now demand components with the highest processing and communication rates (low latencies and high bandwidth, often both simultaneously) and highest capacities with extreme requirements for advanced packaging solutions at both the component level and system level. Insatiable demands have been projected for heterogeneous compute, memory, storage, and data communications. Interconnect has become one of the most important pillars of compute for these systems.

If the taxonomy of interconnects within data centers are examined, the off-package interconnects include network interconnects (4-8 lanes) which are latency-tolerant, and load store interconnects (hundreds of lanes) which are latency sensitive. On-package die-to-die interconnects for load store (tens of thousands of lanes) are extremely latency-sensitive.

Load store interconnects should be thought of as a continuum and needs to scale from die to package to board level and finally to node level.

Continued advancements and application of artificial intelligence (AI) is critical to enhance the functionality and reliability of future components and systems. There are three important areas that need to be supported to enable AI server data centers: AI-based CPU/GPU components, HBM memory components, and AI server/storage systems.

To read this entire white paper, click here.

Devan Iyer is chief strategist advanced packaging for Global Electronics Association. He can be reached at DevanIyer@electronics.org.
Matt Kelly is chief technology officer for Global Electronics Association. He can be reached at  MattKelly@electronics.org.