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A History of Signal Integrity: One Man's Perspective

When I started my career in electronics, there weren’t many signal integrity issues related to PCBs. Heck, there weren’t many PCBs! In the beginning, you could literally layout a PCB with an X-Acto knife and do the chemistry in the kitchen sink. Some of us remember that RF (at that time) was 1.0 megahertz, right in the middle of the AM broadcast band.

Since then, PCB technology has become evermore complex, and circuit speeds have become faster and faster, so that today signal integrity issues are a routine concern for many (if not most) of us.

In my mind, the signal integrity issues as related to PCBs have progressed through 4 stages. Those stages are listed below. The first one is trivial, and I list it only for continuity purposes. The rest of the column will describe the other three.

Stages of Progression for Signal Integrity

Stage 1: No signal integrity issues.Stage 2: Issues caused by, or related to inductance.Stage 3: Issues caused by the fact that resistance is no longer a constant with frequency, but it varies as a function of frequency.Stage 4: Critical lengths are now so short that it is extremely difficult to implement solutions, even if the problems are known.

The Root Cause of the Progression One single parameter is driving the industry from one stage to the next: Faster and faster rise times. 

Stage 2: Inductance

The inductance of traces on PCBs is pretty low. Normally we do not have to be concerned about the inductance associated with a trace until the rise time of the signal gets really short. How short? Well, the formula for the voltage caused by inductance is pretty straightforward:

V = L * di/dt                       Equation 1

People who have taken calculus will recognize this expression. If you do not, then assume the “d” stands for “delta” or “change.”  V is the induced voltage, L is the inductance, di is the change in the current (i.e., the switched current), and dt is the rise (or fall) time of the signal. On a PCB, L is pretty small, as small as 10-8 or 10-9 Hy. Even di is pretty small, unless we start talking about hundreds of thousands of transistors switching at the same time, as in a large microprocessor. So V would be small unless dt is also very small. If we are talking about a rise time of a nanosecond, then dt is 10-9, and suddenly V begins to matter! So the answer to “How small?” generally depends primarily on the rise time of the signal and secondarily on the amount of current being switched.

The root cause of inductance is the changing magnetic field caused by a changing current flow (see Note 1.) It is the inductance itself, or the changing magnetic field related to the inductance, that causes most of the effects in Stage 2. Effects fall into one of four categories: EMI, crosstalk, ground bounce on the power distribution system, or signal reflections.

Although some disagree with me, I argue that EMI and crosstalk are fundamentally the same thing. If the victim trace is far away we call it EMI; if it is close by we call it crosstalk. Both are caused by the electromagnetic coupling caused by the inductive current loop of the signal during very fast switching times (with really no need to talk about whether we are concerned about near-field or far-field effects.)

And the solutions to EMI and crosstalk are the same: Route the traces as close as possible to a continuous, related underlying plane, and separate the aggressor and victim traces as far as possible. Since EMI can also be caused by inductive noise loops on planes, an additional solution for EMI is the use of power and ground (i.e., return) planar pairs for planar capacitance.

Ground bounce is caused by a fast switching current seeing some inductance. For example, if a logic gate switches between logic levels, there is a sudden change in current. If thousands of gates switch simultaneously, there can be a pretty healthy change in current. And this change can happen in less than a nanosecond. If there is inductance in that path (say at the pad where the IC connects to the PCB), then a sudden noise voltage spike can exist at that point. That in turn can (and probably will) add to the signal voltage.So the next logic gate in the signal path sees not only the signal but also a noise spike superimposed on top of it. If the noise spike is great enough, logic errors can result. (You will note that I am describing the phenomena known as “ground bounce” here.)

The solution to this problem is the design of an adequate power distribution system (PDS). (See Note 2.) Fundamentally, it involves the judicious use of bypass capacitors, low-inductance vias and pads, and power and ground planar pairs for planar capacitance.

Reflections are indirectly related to inductance. When any signal propagates down a trace, it reflects back (except in one very special case.) The fundamental question is whether or not we care about the reflection. If the reflection interferes with the signal, such as by interfering with the subsequent bits being sent down the trace, then we care. But if the reflection is not going to interfere, then we don’t care.

Whether or not we care generally depends on the relationship between the rise time of the signal and the propagation time of the signal down the trace--and back. If the signal comes back really quickly (before subsequent bits are transmitted), then we probably don’t care. But if it takes a relatively long time for the reflection to get back, then we might care.

We often talk about the “critical length” of a trace. This is not a precise concept, but the critical length is usually considered to be the length where the “round trip” propagation time (down and back) is equal to the rise time of the signal. (See Note 3.) For traces shorter than the critical length, we usually don’t need to worry about the reflections. For traces longer than the critical length, we might want to take the possibility of damaging reflections into consideration.

The solution to the reflection problem is to use controlled impedance traces, and then terminate them in their characteristic impedance. Controlling the impedance of a trace means controlling the inductive path of the current loop. That is done with the geometry of the trace. Fundamentally, it involves controlling the width of the trace and its separation from its continuous, relevant underlying plane (and also controlling the dielectric properties of the material between the trace and the plane.)Stage 3: Resistance as a Function of Frequency

Most of us have understood that resistance is constant with frequency. It is only inductive or capacitive reactance that varies with frequency (see Note 4). That is true, up to a point. But there comes a time when the resistance of traces on a PCB does start to change as a function of frequency.

The reason this happens is twofold. First, the skin effect begins to come into play (see again Note 1.) Skin effect reduces the apparent cross-sectional area of the trace at higher frequencies. Since the resistance of a conductor is inversely proportional to its cross-sectional area, the resistance of the trace increases for higher frequencies. Clock and data signals are rarely single-frequency sine waves. Instead they more closely resemble square waves and carry many harmonics besides the fundamental frequency. The higher harmonics face higher resistance than do the lower-frequency harmonics, so the waveform is distorted as it travels along the trace. For those of you familiar with “eye” diagrams, the manifestation of this problem is a closing of the eye.

The second problem is dielectric absorption. Think of the dielectric as consisting of a gazillion atoms grouped together in molecules. Inherent in this structure are electrons surrounding the atoms. The electrons are attracted to positive charges and repelled by negative charges. Alternating current acts like alternating charges (caused by the changing electric field around the trace.) The electrons are in constant motion, being alternatively attracted to and repelled by the signal is it propagates down the trace. The actual movement is miniscule. But there is a force exerted on the electrons that tries to move them. A sort of friction holds them in place, and the combination of the forces and the friction results in heat. It is a form of power loss.

Now, where does the power come from? The signal. A little bit of power is absorbed from the signal because it is lost to the internal friction in the dielectric. Because this effect is stronger at higher frequencies, the higher-frequency signal harmonics lose more power than do the lower-frequency signal harmonics. The net effect is the same as with the skin effect--the higher frequency harmonics of the signal are attenuated with respect to the lower-frequency harmonics. In fact, from a signal measurement standpoint, it is almost impossible to separate these two effects, although we can do so theoretically quite well.

The solution to this signal integrity problem is to restore the balance between the lower-frequency harmonics and the higher-frequency harmonics. We can do that by amplifying the higher-frequency harmonics (with an active amplifier), or attenuating the lower-frequency harmonics (with a passive high pass filter.) And we can do either at the beginning of the trace (pre) or at the end of the trace (post). This results in four possibilities: Pre or post, active or passive equalization.

The board designer plays only a minor role here. The real responsibility lies with the circuit design engineer who must select the type of equalization scheme to use (active or passive) and where to place it (pre or post.) The board designer then implements that decision.

Stage 4: Very Short Critical Length

Perhaps you are already aware that the generally accepted critical length for a 1.0 nanosecond rise time (approximately 300 MHz signal) is 3 inches. It works out that the critical length for a 5 GHz signal (75 picosecond rise time or so) is on the order of a quarter of an inch. There is simply not enough room to place effective trace terminations, pads, and vias in such a short region. So the question becomes: What can we do when we get to these very short critical lengths?

While the industry has rules of thumb that are generally accepted for solutions to Stage 2 and Stage 3 issues, we are not in agreement on what to do with Stage 4 issues. One way to see that is to review the conflicting design rules issued by different component suppliers in their application notes, and as written by different authors in different articles. A great deal of attention is being paid to standardizing well-behaved low-inductance controlled-impedance pads and vias, and to component and even package design. 

In any event, Stage 4 is where today’s action is. If you have not reached this stage with your designs yet, perhaps you are lucky. But someday you will!

Notes

1. I describe this in some detail in my article “Skin Effect” which can be found at http://www.ultracad.com/article_outline.htm.
2. See my column on “Calculating PDS Impedance,” at http://www.pcbdesign007.com/pages/columns.cgi?clmid=55&artid=70670.
3. Interestingly enough, there is also a critical length associated with crosstalk. It is when the propagation time of the length of the coupled region equals the rise time of the aggressor signal. It is this length where the backward crosstalk signal reaches its maximum amplitude. Backward crosstalk amplitude starts small and increases with coupled length up to the critical length. For coupling regions longer than the critical length the backward crosstalk pulse width continues to widen, but the amplitude of the backward crosstalk pulse stops growing.
4. See my columns on “Resistance, Reactance and Impedance” Parts 1, 2, and 3 at http://www.pcbdesign007.com/pages/columns.cgi?clmcatid=&clmid=55.

Douglas Brooks has an MS/EE from Stanford University and a Ph.D. from the University of Washington. He has spent most of his career in the electronics industry in positions of engineering, marketing, general management, and as CEO of several companies. He has owned UltraCAD Design Inc. since 1992. He is the author of numerous articles in several disciplines, and has written articles and given seminars all over the world on Signal Integrity issues since founding UltraCAD. His book, Printed Circuit Board Design and Signal Integrity Issues was published by Prentice Hall in 2003. Visit his Web site at www.ultracad.com.