Global Technology Development: HDP User Group European Meeting 2016

Estimated reading time: 16 minutes

Mike Freda from Oracle reported on the second phase of the High Frequency Test Methods project.

It had previously been observed that the moisture content of laminate could significantly affect the measured values of Df and Dk at frequencies in the range 1 GHz to 20 GHz and above. A better set of data, that included moisture as a variable, was needed and the proposal for this phase of the project was to evaluate the effect of moisture on high frequency Dk and Df test methods. The materials selected for testing were lower-loss laminates known to be capable of absorbing significant amounts of moisture, although materials containing fillers such as aluminium trihydrate, which could break down at high temperatures and release water, were excluded. A preliminary pilot run was planned, using Megtron-6, to evaluate the moisture content test protocol using Z-axis type test methods, prior to building test boards from four other materials, and moisture content would be the main variable for the Dk and Df testing. Samples would be pre-conditioned to four moisture contents:  as-is, high, medium, and dry, with weight-gain coupons included to enable micro-balance determination of approximate moisture content for each Dk and Df measurement. Eighteen collaborators were cooperating in the project, and final results were expected to be reported in October 2016.

Against a background of BGA pitches trending downwards from 1 mm and 0.8 mm to 0.5 mm and 0.4 mm, consumer electronics using thin any-layer-via (ALV) HDI PCBs to support very fine-pitch BGAs with large arrays, data transmission speeds increasing through the 40GHz to the 100GHz level, and PCB routing and via and BGA pad densities continuing to increase, facilitator Jack Fisher described the Future HDI project, which was at the definition stage. The project set out to apply stacked any-layer-via (ALV) technology to very thick boards and provide data on performance and reliability for the benefit of the telecom/server and aerospace/defence sectors. The test vehicle design was an 18” x 24” panel with 10-layer stacked sintered-copper-paste ALVs on each side of a 4-layer core. This would be offered to six fabricators to build, but the individual fabricators would be free to use their own preferred methods of construction. Test vehicle definition was complete and panel layout design was in progress. Fabrication was due to start at the end of June 2016 and aimed to be completed in time to commence testing on 30th September. Testing would include measurement of current carrying capability, lead-free survivability and IST reliability, CAF susceptibility, electrical performance and component interconnect reliability.

Alun Morgan described the objectives of Phase 5 of the Lead-free PWB Materials Reliability project, currently at the definition stage. Potential issues resulting from lead–free SMT reflow included internal and surface delamination, CAF failure, through-hole plating failure and pad cratering, all of which were more acute at higher peak reflow temperatures. The project goal was to assess the impact of the lead-free soldering process on latest-generation PWB laminates, with a focus on their suitability for high layer count / high thermal mass design applications in which board surfaces could be subject to peak reflow temperature up to 260°C. 64 materials had been tested to date, and proposed candidate materials for the fifth phase represented a wide spectrum of loss characteristics, from no low-loss requirement through semi-high-speed and Tier I to Tier IV high-speed classifications, all the way to Tier V ultra-low-loss ceramic-filled PTFE. The primary project deliverable would be a final report, to include all empirical data along with analysis, conclusions and recommendations for future work, and the working team would consider publication of anonymised data from the project if deemed appropriate. Nineteen companies were participating in the project, and the target date for the final report was end of December 2017.

Professor Dr.-Ing. Klaus-Dieter Lang, Head of the Fraunhofer Institute for Reliability and Microintegration in Berlin, gave the guest presentation on advanced microelectronic and microsystems assembly and packaging, and discussed technology strategies for system integration of microelectronics and microsystems in the development of Smart Systems.

The major challenge was that every “smart” electronic systems application required its own technology path and specific solution, and the main considerations in system integration strategies were performance improvements, multiple functionality, adapted form factors and highest system reliability, as well as energy efficiency and cost reduction.

As microelectronics packaging continued to evolve, and the gap between silicon and HDI PCB processing capabilities and feature sizes became ever wider, the real revolution was inside the package, and the amount of functionality that the package could contain. There was a wide range of options for packaging platforms, from the substrate-less fan-out wafer level package (FOWLP) through advanced substrates with silicon, glass, organic or hybrid interposers, to embedded die, and some of these were already established at panel level.

The fan-out wafer level package was a means of interconnecting from 40–100 micron pitch at the die to 0.4-0.5 mm pitch at the PCB without using an interposer, and hence offering a significant cost saving. Professor Lang described and compared the process flow options for FOWLP and fan-out panel level packaging (FOPLP). The mould-first option was preferred by the silicon manufacturer, the RDL (re-distribution layer)-first option was preferred by the packaging company. Enormous growth was forecast in FOWLP on 300 mm wafers, mainly in the smart-phone sector - for example, the original iPhone had two FOWLP devices; the iPhone 6 has 26 FOWLP devices.

Wafer-level system integration technology offered improvements in integration density, and reduced interconnect length led to improved transmission speed and power consumption, together with reductions in system volume, weight and footprint. The functionality of microelectronic systems was driven by applications, and examples were image sensors, memory stacks, processor/memory modules, sensor nodes and RF devices. However, the technology required a clean-room infrastructure similar to that found in semiconductor production, the cost of which put it out of the reach of smaller manufacturers.

Considerations in panel-level system integration solutions included high-density wiring, thermal management, thin chip handling and assembly, ultra-thin interconnects and embedded actives and passives. There were applications in sensors, logic and power management. Professor Lang described and compared face-up and face-down process alternatives for chip embedding, with reference to the sensor integration line installed at Fraunhofer IZN, and showed an example of panel level embedding for the wireless mobile phone charger integrated into certain Audi models. Market forecasts predicted exponential growth in embedded die activity, principally in the mobile wireless and consumer sectors.

“Dual Integration” was the intelligent combination of wafer-level and panel-level technologies to fill the gap between wafer and PCB infrastructures, and Professor Lang described a modular micro-camera for an internet-of-things application, which incorporated 72 embedded components including a 32-bit microprocessor, all within a 16 mm x 16 mm x 3.6 mm package. The camera was manufactured in quarter-panel format, 12” x 9,” 77 modules per panel, with double-sided component assembly on the inner layer, embedded by prepreg lamination.

Future smart-system development challenges included integrated multifunctionality, by combining electrical, optical, mechanical, biological and chemical processes, system integration for harsh-environment applications, improved system reliability through material and technology optimisation, and enhanced design tools for the combination of system functionality and assembly technology. And, of course, manufacture for low or reasonable cost.

Page 2 of 3

• < Previous Page
• Next Page >