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As the semiconductor industry approaches the end of the second decade of the 21st century, substantial changes to the System-on-a-Chip (SoC) design methodology are taking shape. Instead of dealing with SoC design at the lowest common denominator – the discrete SIP block, SoC designers now look to move up a layer of abstraction to design with system level functionality to reduce the effort and cost associated with complex SoC designs today. The IP subsystem is the evolutionary step designers are employing to infuse the right level of complexity, functionality and performance to meet quickly changing market requirements without experiencing a corresponding increase in design effort or design cycle time. A new research report from Semico , The IP Subsystems Market: An Evolving Landscape, forecasts that the CAGR for all IP Subsystems will reach 17.6% by 2020.
"Most of these evolutionary forces are driven by the need to integrate more functionality in fewer devices at the system level and in ever-smaller system footprints", says Rich Wawrzyniak, Principal Analyst. " One method to accomplish this is through the use of 3rd Party SIP. However as design costs and time to market pressures mount on SoC designers, it is becoming more and more difficult for these designers to accomplish their tasks in a timely and cost effective manner. This then sets the stage for the next evolutionary leap in the semiconductor market and SoC design landscape with the introduction of the IP Subsystem. In addition, there is evolution occurring within the IP Subsystem market itself as new types of subsystems enter the market, even with the introduction of the first 'distributed' subsystems within the design landscape."
Key findings of this new research include:
- The Americas market will experience strong growth over the forecast period to $320.8M by 2020.
- The Chinese market will have a CAGR of 17.8% through 2020.
- Value Multicore SoCs are the second-largest user of IP Subsystems, reaching a CAGR of 23.0% by 2020.
- More IP Subsystems are being introduced with internal interconnects or sophisticated bus structures to make the highest level of performance available to the designer and user.
