Six Keys to Design Excellence: Combating PCB Complexity

Estimated reading time: 7 minutes

This month, we will look at another major issue in today’s PCB design and development: PCB complexity.

Many companies are finding that the evolving and ever-increasing complexity of PCB designs are the number one concern for new product introduction. So many things can go awry with an extremely complex PCB that the associated risk is one of the greatest of the development process. When companies effectively deal with making complex PCBs right the first time, on-time delivery and income for that product is maximized. But when companies fail to deal with complex PCB issues, their product can be delayed, cost significantly more than projected, or they may miss the market window.

Mentor Graphics has sponsored the Technology Leadership Awards program for more than 20 years. During that time, the data collected has shown some interesting trends. Figure 1 shows the trends for number of components on the average PCB design submission, and the average number of pin-to-pin connections. Using these two factors, it’s pretty clear that complexity continues to increase, and at an advancing rate.

But there is another factor that cements the fact that complexity is increasing rapidly: The average area for the PCB design submissions has remained about the same for the twenty-plus years. So, while the board size has been constant, the number of components has more than quadrupled. Clearly, there is a complexity problem to be dealt with.

Figure 1. Using “number of components” and “pin-to-pin connections” as indicators of complexity shows an ever increasing trend that is increasingly upward.

Speed and Power

While the statistics just presented are compelling, they are static. On the dynamic side is the similar rapid increase in operating speed of circuits. With these increases in speed come problems with signal integrity and EMI, plus the higher speed devices can require more current and run hotter, creating power integrity and thermal management problems.

Unlike a short time ago, when all ICs ran on +5 volts so power to the board could be accommodated on a single voltage and ground plane, today’s PCBs have several different voltages that can be as low as 0.9 VDC. All of these power distribution networks--one for each voltage--must be incorporated into the PCB…and of course, please don’t add any layers! This fragmenting of voltage planes can also induce power problems, so power integrity must be examined for each voltage, and both AC and DC components.

Manufacturability

As boards become more complex and carry faster signals, coupled with shorter and shorter development times, a need has arisen to ensure that a board is manufacturable from the very start, avoiding costly, time-consuming re-spins to correct errors. Finer tolerances, smaller components, denser BGAs and even flip chip mounting all contribute to the need for checking for manufacturing violations, best practices for higher yields and increasing long term product reliability. But these rules can be very extensive (over 700) and beyond the comprehension of the average designer to track during layout.

High-Pin-Count Packages

Just like PCB complexity, ICs are packing much more functionality into smaller packages…with more pins, closer together. That combination makes routing from those dense BGAs into the rest of the PCB a difficult task. First the package is laid out from the surface BGA pads into the inner layers of the PCB (fanout). Next is to breakout from those inner layer vias and interconnect to the rest of the components on the PCB. Without CAD tools, this process can take a layout designer days of interactive routing.

With the CAD tools now available, the fanout and breakout process can be automated where the routing takes minutes versus days. The first step is the fanout. This can be done either using HDI/microvia layers or through-vias. The actual fanout takes seconds with an automated function.

Two possibilities exist for starting the breakout:  “North-South-East-West”  using layers and escapes to the nearest edge of the BGA, or a “layer-biased” pattern where the breakouts go in the direction of the interconnect and are biased to layer direction. Figure 2 illustrates both.

Figure 2. Illustrations of both the North-South-East-West and the layer-biased automated breakouts.

Simulation

Advances in IC density and performance have downstream affects on PCB design. First is the large number of high-speed interconnects that must be finely tuned for delay, crosstalk and signal integrity. An additional requirement is to virtually prototype (simulation and analysis versus building and testing a prototype) the critical signal corner cases to make sure they meet spec at extreme temperature and manufacturing tolerances.

Advanced design systems have a seamless methodology that enables an engineer to pre-analyze the high-speed nest classes and set up a set of constraints for those interconnects. These constraints are carried through the rest of the design system and available to the layout and the post-layout analysis steps. During layout, whether the CAD design is performing interactive or automatic routing, the constraints are followed to meet the length (delay), parallelism (crosstalk) and tolerance (matching) specs. With boards with a high number of constrained interconnects, this automated functionality provides the productivity and accuracy to produce a correct board the first time, on time.

The second high-performance issue is heat and how to manage it. If the junction temperature of an IC goes over spec, the IC suffers both reduced performance and long term reliability issues. But solving the heat management problem is a multilevel (Figure 3) task. The IC package must be designed to provide adequate heat dissipation to its extremities. The PCB is affected by how close and where you place the hottest components.  And it all comes down to the complete product’s power dissipation capabilities including the enclosure, fans, heat sinks, rails, etc. There are very few tool suppliers who are capable of providing thermal analysis solution at all three levels required, especially since the analysis at the full system level is typically performed by a mechanical engineer, with PCB data supplied by the PCB designer plus the MCAD design of the enclosure. If virtual prototyping thermal analysis is not available, the option is to build real physical prototypes, test them and then make design changes. This is a very time-consuming and costly process.

Figure 3. An integrated simulation system not only provides solutions for signal and power integrity, plus thermal analysis, but goes way beyond by showing the interrelationships. Here, HyperLynx shows the thermal effects of a high current density area of the PCB.

The third issue is the design of the power distribution networks to support the multiple and low-tolerance voltages required to support the ICs. As CAD designers jigsaw these complex PDN shapes into the limited PCB layers, they may believe that they have supplied adequate copper to support the DC requirement of voltage levels and low-current densities.

However, through-vias and pins might reduce the effective amount of copper at neck-down points. DC power integrity analysis functionality can accurately analyze the PDN and highlight potential problem areas which can be fixed with additional copper of vias to carry the currents. Another issue with PDNs is clean voltages supplied to the ICs. This AC affect originates from multiple IC power pins switching simultaneously and basically causing your PDN to act as a transmission line and produce unclean voltage levels. The power integrity analysis function can tell you where to add decoupling capacitors, thus supplying clean and adequate voltages throughout the PDN.

Manufacturability

Design for manufacturability (DFM) is not just looking for and correcting design violations that will cause production failures. You must also strive for high fabrication and assembly manufacturing yields (product cost and reaching target volume production levels) and high, long-term product reliability. But it is impossible for a designer to understand and follow as many as 700 rules and best practices manually. For this purpose, software exists that can perform those checks during the design process. This software is embedded in PCB layout products like Mentor’s Expedition Enterprise. It is executed periodically during the layout process and provides cross probing that highlights DFM errors for correction right in the layout environment, as shown in Figure 4, using Mentor Graphics Valor NPI.

Figure 4. DFM uses rule-based examinations of the design to locate and highlight potential manufacturability problems so that they may be corrected before any physical PCB is made.

Solving the Complexity Problem

Increasing complexity of PCB designs and the associated risk that it brings to product development has created some difficult challenges. The solution to “first-time-right” PCB in this complex domain is automation to simulate and identify problems and errors before any hardware is produced. This can save time and costs, not to mention helping to ensure meeting fleeting market windows.

John Isaac is Director of Market Development for Mentor Graphics Systems Design Division. John has worked in the Electronic Design Automation (EDA) industry with PCB and IC technology for more than forty years. John joined Mentor Graphics where he has held marketing positions in both PCB and IC product areas. He is currently responsible for worldwide market development for the Systems Design Division.