MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Estimated reading time: 4 minutes

Morgan State University (MSU) recently received an Apple Innovation Grant, designed to support engineering schools as they develop their silicon and hardware technologies. The New Silicon Initiative (NSI) is designed to inspire and prepare students for careers in hardware engineering, computer architecture, and silicon chip design.

Innovative professors, such as MSU's Dr. Kevin Kornegay and others responsible for delivering on the NSI goals, are leveraging the funding and support to create invaluable, hands-on experiences for their students. MSU faculty can enhance the NSI curriculum by inviting subject matter experts to provide guest lectures on topics such as integrated circuit design and computer architecture, providing practical insight regarding the theory and practice of silicon design. The course sequence starts with "Introduction to Electrical and Computer Engineering" (EEGR 105), where sophomores learn hands-on skills in circuit design, and works up to the critical class in the NSI program: the new "Tapeout Course in Digital Integrated Circuit Design" (EEGR 463). EEGR 463 ran in parallel with a similar course offered at UC Berkeley, where the lectures, assignments, and labs were the same, and the UC Berkeley instructors were in lock step with the teaching assistants at MSU.

“In collaboration with UC Berkeley and industry partners Cadence, Intel, and others, students enrolled in my EEGR 463 course at MSU are getting invaluable hands-on experience designing chips from RTL to fabrication. By leveraging the Intel 16 and the Cadence tool flow, including Genus, Innovus, Tempus, and Pegasus technologies, students take their ideas from concept to reality, setting themselves apart from others looking to launch a career in the electronics industry,” said Kevin Kornegay, Eugene DeLoatch Endowed Professor in IoT, Department of Electrical and Computer Engineering, Morgan State University.

Tapeout is the final design process before a circuit is sent for manufacturing, so in this course, student teams create the design specification and implement the physical design and verification for tapeout. Students in Dr. Kornegay's course had a successful VLSI tapeout using the Intel PDK and leveraging the Cadence-based tool flow to create a chip from idea to implementation using Intel's 16nm FinFET technology chip fabrication facility. This success indicates the impact funding can have and how it will be instrumental in getting these students positions with leading companies in the industry.

In addition to funding, it's essential for companies to make technology that is consumable in a shorter period so that students can learn and implement it in a semester or two. The Intel 16 class node is an ideal gateway to FinFET. It uses fewer masks with simpler back-end design rules and is supported by all leading electronic design automation (EDA) and IP companies, including Cadence. However, what sets Intel's University Shuttle Program apart for academia is that it offers access to industry-standard processes like Intel 16 and the upcoming Intel 18A, so students gain practical experience before launching their careers.

“Intel was glad to provide our PDKs to the MSU students so that they could fabricate their ideas on one of our latest processes, ensuring that students are familiar with the same processes that we and our customers utilize, setting them up for success as new college graduates in the industry,” said Bryan Casper, Senior Principal Engineer, Intel Corp.

Cadence is passionate about enabling academia to cultivate the next generation of innovators by making all the tools needed for the design flow readily available in the classroom and lab, including support for the different industry tools that make it possible for students to gain real-world experience, such as the Intel 16 Custom/Analog Flow. Cadence's Virtuoso Studio, which consists of the Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso ADE Suite, and the integrated Spectre X Simulator, has been certified for Intel 16 technology. These tools have all been enhanced to better manage corner simulations, statistical analyses, design centering, and circuit optimization.

In addition, Cadence design IP has been ported and silicon-tested for Intel 16 technology, including PCI Express (PCIe) 5.0; 25G-KR Ethernet multi-protocol PHY; multi-protocol PHY for consumer applications supporting standards such as PCIe 3.0 and USB 3.2; multi-standard PHY for LPDDR5/4/4X memory; and MIPI D-PHY v1.2 for cameras and displays. Collaboration across industry and academia will impact the electronics industry workforce and the future of technology.

“Cadence is proud to partner with MSU and appreciates the work done in the labs to foster the next generation of semiconductor engineers. Having new college graduates with experience using the same commercial tools, flows, and processes as many of our customers enhances their productivity as incoming silicon chip designers,” said David Sallard, Senior Principal Application Engineer, Cadence.

With an investment of time, money, and technology from industry and academia, we can effectively foster the next generation of innovators to address the workforce shortage impacting the entire industry. The professors at MSU have proven that this is a recipe for success. Congratulations to the students who successfully sent a chip for tapeout and to the professors, teaching assistants, and industry experts who played a role in making that happen. It's only a matter of time before these students are transforming the future of technology.