Underfill Design and Process Considerations

Estimated reading time: 11 minutes

By Steven J. Adamson

The effective use of underfill requires a blending of many factors, including product-design issues, to accommodate the dispensing process and product Imperatives. As circuit densities have increased and product form factors have diminished, the electronics industry has spawned a variety of new methods for integrating chip-level designs more tightly with board-level assemblies. To a great degree, the emergence of technologies such as flip chip and chip scale packaging (CSP) have effectively blurred the traditional lines of demarcation between semiconductor die, chip packaging methods and printed circuit board (PCB) assembly-level processes. While the advantages of these new high-density, chip-level assembly techniques are quite significant, choosing the best technology options and achieving consistent and reliable production results is becoming increasingly difficult as smaller dimensions make components, interconnections and packages more susceptible to physical and thermal stresses.

One of the key technologies improving reliability is the use of underfill materials between the die and substrate to help distribute stress from thermal gradients and physical impacts. Unfortunately, clear guidelines have not yet evolved regarding when to use underfill and how best to adapt underfill methodologies to specific production requirements. In this article, some of the current thinking on these issues will be explored.

Why Underfill?

The primary reason for considering the use of underfill encapsulant is to reduce the impact of mismatches in global thermal expansion characteristics between the silicon die and the underlying substrate to which it is attached. With conventional chip packaging, these stresses are typically absorbed by the natural flexibility of the wire leads. However, with direct-attach methods such as solder ball arrays, the solder joints themselves represent the weakest points in the structure and therefore are the most susceptible to stress failures. Unfortunately, they are also the most critical because a failure at any interconnect point destroys the functionality of the circuit. By tightly adhering to the chip, solder balls and substrate, the underfill material redistributes the stresses and strains from the coefficient of thermal expansion (CTE) mismatch and mechanical shock over the entire chip area.

Secondary benefits from underfilling are protection against moisture and other forms of contamination. On the negative side, the use of underfill adds cost to the manufacturing operation and makes rework difficult. Because of this, many manufacturers conduct a quick functional test after reflow and prior to the underfill operation.

Deciding When to Underfill

Because there are more than 50 different designs of CSPs1, plus a myriad of variables and operating conditions involved in interconnect design, it is difficult to provide a definitive rule-of-thumb for when to use underfill. However, there are a number of key factors that should be taken into account when designing PCBs. Some of the critical factors include:

• Differences in CTE between the die and substrate. Silicon has a CTE of 2.4 ppm; typical PCB material has a CTE of 16 ppm. Ceramic materials can be designed to have a matching CTE but 95 percent Alumina ceramic has a CTE of 6.3 ppm. The need for underfill is greater on PCB-based packages, although increased reliability has also been demonstrated on ceramic substrates. An alternative approach is to use an interposer substrate, such as a high-CTE ceramic or flexible material, as a shock absorber between the chip and the main substrate, which can mitigate the CTE differences between PCB and silicon die.
• Die size. Generally, the larger the die area, the greater the strain-induced problems. For example, one study has shown that when die size increased from 6.4 to 9.5 mm, the number of temperature cycles from -40° to 125°C that the interconnect could tolerate decreased from 1,500 to 900 cycles.2
• Solder ball size and layout play a key role in the underfill evaluation because larger ball sizes, such as those 300 µ in diameter that are typically used with CSPs, are more robust and can handle strain better than the 75 µ diameter balls used with flip chips. Assuming the relative sheer strain displacement of a two-member joint is similar for CSP and flip chip, then strain experienced by the CSP solder joint is approximately a quarter of that experienced by a flip chip. Therefore, CSP designers originally thought that the solder ball structure itself could handle the mechanical strains associated with substrate and die thermal expansion. Subsequent studies2 have shown underfill offers a significant reliability benefit with CSPs, particularly in portable applications. On the layout issue, some designers have found that increasing the size of the lands at the chip corners can increase strain resistance, but this option is not always practical or sufficient to achieve reliability goals.
• System PCB thickness. Experience has shown that thicker PCBs are stiffer and resist bending forces from impact shock more than thinner boards. For example, one analysis has demonstrated that an increase of FR-4 substrate thickness from 0.6 to 1.6 mm could improve cycles-to-failure from 600 to 900 cycles.3 Unfortunately, the reality in many of today's ultra-small devices is that it is often impractical to increase substrate thickness. In practice, each doubling of substrate thickness provides approximately a 2X improvement in reliability, but a doubling of die size imposes a 4X degradation.4
• Use environment. In the final analysis, the overriding factors generally have to do with increasing expectations for survivability. For example, it is becoming common for the specifications for hand-held devices (cell phones, pagers, etc.) to call for normal functioning after thermal cycling between -40° to 125°C for 1,000 cycles and survivability after 20 to 30 drops from 1 m onto a concrete floor.

Figure 1. Underfill dispensing on substrates with closely spaced components.

Research on thermal cycling has shown that the use of underfill can provide a 2 to 4X increase in the number of -40° to 125°C temperature cycles that can be handled prior to exhibiting failure modes, with some underfilled assemblies still not failing after as many as 2,000 cycles.5 When weighed against the actual costs of field failures (e.g. returns, loss of reputation, etc.) for devices exposed to increasingly harsh environments, many manufacturers are actively turning to underfill as a reliability insurance policy.

Dispensing Challenges

Once the decision has been made to underfill, a number of challenges must be taken into account to efficiently implement the process to achieve consistently reliable results while maintaining required production throughput levels. Some of these key issues include:

• Achieving complete and void-free flow under the die
• Dispensing around closely packed die
• Avoiding contamination to other components
• Dispensing through openings in radio frequency (RF) enclosures or shields
• Controlling flux residues.

Achieving Complete and Void-free Flow

Because the underfill material must be drawn under the die through capillary action, it is vital to position the needle close enough to the die to start the flow. Care must be taken to avoid touching the chip or contaminating the back side of the die. A recommended rule of thumb is to position the needle starting point at an X-Y offset of one-half the needle's outside diameter plus 0.007", and at a Z height of 80 percent of the chip height from the substrate. Precision control is also required throughout the dispensing movement to maintain flow without damaging or contaminating the die.

For optimal throughput, it is often desirable to dispense on multiple sides of the die in a single pass. However, opposing fluid wave fronts that meet at an acute angle can create voids. The dispensing pattern should be designed to create wave fronts that only converge at oblique angles.

Die Number and Proximity

When designing a board where closely packed die are to be underfilled, the board designer needs to leave adequate space for the dispense needle. Two die sharing a dispense path as shown in Figure 1 at position 1 is an acceptable dispensing practice. Passive components running parallel with the edge of a device, as in Figure 1 at position 2, will act as a dam. Components that are positioned 90° to a die edge tend to pull fluid away from the device to be underfilled. Underfill material surrounding passive components has not been found to have a deleterious effect. Cross-capillary action from adjacent chips or passive components that pull the underfill material away from the intended device can result in voids under the CSP or flip chip.

Figure 2. Underfill dispensing through holes in RF shields.

In most applications, a 21- or 22-gauge needle is a good choice for device underfill. Smaller diameter needles have greater resistance fluid flow, which translates into slower dispensing times. However, it is sometimes necessary to minimize a fillet size by using a small diameter tip to keep fluid away from other components (Table 1).

Sometimes it is possible to deal with these problems by using a multi-head dispensing system to pre-dispense a dam around the adjacent component using a higher viscosity material that will not flow beneath it. During the subsequent dispensing pass, the dam effectively prevents any unintended capillary flow from going under the adjacent device.

Dispensing Through Openings

With underfill increasingly being used in RF assemblies, the dispensing process is often challenged to apply the underfill after an RF shielding enclosure has been put in place. For optimal production efficiency, it typically makes sense to position the RF shield during the same pick-and-place process as the other components and to solder everything in a single reflow pass. Therefore, the product and process designers must collaborate to leave adequate openings in the shield for underfill dispensing, without defeating the efficacy of the shield itself. The designers also must avoid placing the die too close to the RF shielding because capillary action or dispensing at a high rate might allow the underfill to flow up the inside of the RF shield and over the CSP or flip chip. If the gap between the devices and the shield is small, the rate that underfill material is dispensed will have to be limited to avoid filling above the device. Slowing down the dispense rate will slow the assembly process, limiting throughput. This can be somewhat offset by moving to another hole or device and returning to the first hole to dispense more fluid. However, this involves multiple moves, which again lowers throughput (Figure 2).

An equation developed for underfill flow rate is given by Schwiebert & Leong.7

Time to flow is given by:

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Pumps and valves from most manufacturers can deliver fluid to a CSP or flip chip quicker than the material can flow under the die. The volume/weight of fluid under the die will need to be determined.8 Once these numbers are determined, make a first approximation on the flow rate and decide if all the fluid should be put down in one dispense or multiple small amounts. A typical process is: while fluid is flowing under the first device, move to second device, dispense and return to the first location to finish. For example, if the amount of material under the first device is 20 mg and it is split into two dispense cycles, a dispensing system that can deliver 10 mg amounts accurately is mandatory.

Controlling Flux Residue

Experience has shown that the presence of excess flux residue can negatively impact the underfill process. This is because the underfill adheres to the flux residue rather than adhering to the solder balls, die and substrate as intended, resulting in voids, streaking and other inconsistencies. While some research6 has shown that cleaning under the die before dispensing underfill can show a thermal cycling improvement of as much as 5X, in reality, adding such a process runs counter to current industry trends and also negatively impacts overall throughput. A much more practical alternative is to provide better process control over the fluxing operation through techniques such as selective jet fluxing. Selective jet fluxing can be especially useful in mixed technology designs using flip chips and CSPs with different ball diameters (75 vs. 300 µ), because the amount of flux at each device site can be software-controlled to provide an exact thickness of flux for each device type.

Optimizing Dispensing Accuracy, Flexibility and Process Control

Accurate and repeatable dispensing of underfill is of prime importance in high-volume production environments, particularly when consistent delivery of ultra-small shot sizes in the 10 mg range is required.

Underfill dispensing requires precise pumping action where flow rate never varies with changes in the viscosity, needle diameter, etc. Accurate volumetric control of underfill fluids can best be achieved through the use of a true linear positive-displacement (LPD) pump using a piston to always displace the exact volumes required, whether in large or small shots. In addition, the dispensing system needs to incorporate closed-loop feedback, using highly accurate gravimetric measurements to provide precision real-time control over the amount of fluid being dispensed. Finally, the dispensing system has to incorporate high-precision, programmable motion systems that enable the flexible implementation of a variety of different dispensing patterns, without sacrificing overall throughput.

Conclusion

The effective use of underfill requires a comprehensive blending of many different factors, including product-design issues to accommodate the dispensing process and dispensing process-design issues to accommodate product imperatives. The bottom line is that accurate and flexible dispensing of underfill for the full range of chip-level design requirements must involve a collaborative partnership between the product designer, manufacturing process engineer, fluid formulator and dispensing systems supplier.

REFERENCES

1. John H. Lau and S.W. Ricky Lee, Chip Scale Package, page xvii, McGraw Hill.
2. Dr. Reza Ghaffarian, "Key Factors in Chip-scale Assembly Reliability," Chip Scale Review, November 1998, p. 29-34.
3. Dr. Reza Ghaffarian, "CSP Assembly Reliability," Circuits Assembly, September 1998, p. 40.
4. Communication with H. Quinones, Chief Scientist, Asymtek, November 1999.
5. Dr. Reza Ghaffarian, "Key Factors in Chip-scale Assembly Reliability," Chip Scale Review, November 1998, p. 31.
6. Rod Martins and Michael Roesch, "Large Flip Chip on Laminate Substrates with Microvias," HP, Fort Collins, HDI Conference, August 1999, Mesa, Ariz.
7. M.K. Schwiebert and W.H. Leong, "Underfill Flow as Viscous Flow Between Parallel Plates Driven by Capillary Action," ISHM-USA, October 1995.
8. Asymtek Flip Chip Calculator is available for free from www.asymtek.com or by calling (800) ASYMTEK.

STEVEN J. ADAMSON is the semiconductor packaging and assembly product manager for Asymtek, a Nordson Co., 2762 Loker Avenue West, Carlsbad, CA 92008-6603; (760) 431-1919; Fax: (760) 431-2678; Web site: www.asymtek.com.