Tin Whisker Mitigation Methodologies: Report from SMART Group, Part 1

Estimated reading time: 8 minutes

Cawthorne reviewed the definitions of the mitigation control levels defined in GEIA-STD-0005-2, commenting that the required level would normally be a function of the design authority in consultation with the customer, and that military applications would typically expect mitigation to at least Level 2B—risks managed primarily through mitigations, including design rules, and more likely 2C—risks managed more by avoidance and less by mitigation. Level 3 managed whisker risks through complete avoidance. He went on to discuss the detail requirements of Levels 2B, 2C and 3, with particular reference to the use of conformal coatings to form a physical barrier. The defining standard for tin whisker susceptibility of tin and tin alloy surface finishes was JEDEC JESD201A, an accelerated test used by component manufacturers, but there was some doubt as to the reliability of results since tin whiskering was such an unpredictable phenomenon.

In summary, as the standards had evolved, they had become increasingly definitive with regard to component-to-component spacing design rules. There had been a move away from component termination material type, structure and processing as specific mitigation strategies. Strategies were now based on protective barriers, re-finishing of component terminations, and automatic coverage of pure tin finished surfaces by tin-lead solder during the assembly process.

A series of collaborative projects had been carried out at the National Physical Laboratory to evaluate conformal coating as a tin whisker mitigation strategy for printed circuit assemblies. Martin Wickham reviewed previous findings and gave an update on current work. Using a tin plating process deliberately chosen for it high propensity to whiskering, NPL had developed a parallel plate test vehicle that had been enabled electrical detection of failure. One observation was that failure predominantly occurred at the edges of plates, where full coating thickness was not maintained around the right angle bend, and this geometry was a characteristic feature of component leads. An additional test vehicle had been designed, based on a PCB with 24 SOIC14 packages, assembled using range of techniques, to enable testing for short circuits between adjacent leads on individual component. Each batch of eight boards was delivered to consortium partners for coating and returned to NPL for testing. The assemblies were constantly monitored at a test voltage of 15 volts with a series resistor to limit current to 15 milliamps.

Nine batches had been built to date, together with control assemblies with no coating, all of which had shown extensive whiskering before any evidence was seen on the coated examples. Using the analogue of two sword-fencers for illustration, Wickham explained different failure modes: intermittent shorts involving more than one whisker, and longer shorts penetrating out through the coating in one position and back in through the coating elsewhere. He showed several examples of actual failures, and other instances where whiskers had grown but not yet been detected electrically. It was intended to continue ageing the test vehicles and review failures after a further six months, and to visually inspect the assemblies again after twelve months, also to build control assemblies to investigate the effect of temperature during coating. Possible future work would investigate the effects of vibration and forced air cooling.

In Part 2, SMART Group Steering Committee member Ian Fox, Micross Components’ Mark Walmsley, and more words from Dr Mark Ashworth.

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