-
- News
- Books
Featured Books
- smt007 Magazine
Latest Issues
Current IssueComing to Terms With AI
In this issue, we examine the profound effect artificial intelligence and machine learning are having on manufacturing and business processes. We follow technology, innovation, and money as automation becomes the new key indicator of growth in our industry.
Box Build
One trend is to add box build and final assembly to your product offering. In this issue, we explore the opportunities and risks of adding system assembly to your service portfolio.
IPC APEX EXPO 2024 Pre-show
This month’s issue devotes its pages to a comprehensive preview of the IPC APEX EXPO 2024 event. Whether your role is technical or business, if you're new-to-the-industry or seasoned veteran, you'll find value throughout this program.
- Articles
- Columns
Search Console
- Links
- Events
||| MENU - smt007 Magazine
Reducing Warpage on BGAs During Rework
January 9, 2017 | Bob Wettermann, BEST Inc.Estimated reading time: 3 minutes
One of the challenges associated with BGA rework has to do with effects of device warpage, which can cause undue shorts or opens post rework. The impact of a lead-free rework process, the continuous "thinning" of the BGA package as well as continued turnaround time pressures of rework all have led to increased propensity of this phenomenon to occur. While most of the failures in the rework process can be captured via visual or x-ray inspection, or some escapes in test can occur. For example, head-in-pillow defects can be caused by the process of the ball being “pulled” out of the oriented paste during the reflow profile. Too much warpage can also create stress on the solder ball joints and lead to reliability failures of the packages (Figure 1).
Figure 1: Typical rework profile and the potential impact of warpage at differing points.
Outside of opens and shorts in the reflowed and reworked BGA, there is a widely accepted analytical technique for measuring the degree of warpage. These measurements are made by coating the part with reflective paint and placing a sheet of low expansion quartz glass etched with equally spaced parallel lines parallel to the sample. A beam of light is then directed onto the quartz glass and the lines create a shadow on the top of the BGA package. When the package becomes warped a Moiré pattern is produced by the geometric interference between the lines on the quartz and the shadow of the lines on the surface. These fringe patterns then can be calibrated and are displayed as 3-D topographical part "map". A typical Shadow Moiré warpage output, from a modern measuring instrument, can be seen below (Figure 2). This method tries to emulate the behavior of the package through a thermal cycle.
Figure 2: Shadow Moiré output showing device warpage. (Courtesy: Akrometrix)
The difference among the components in the BGA (silicon die, the molding compound, substrate, etc.) causes thermal stresses due to the thermal expansion mismatch between the various components. A major reason for warping in area array plastic package is this coefficient of thermal expansion (CTE) mismatch. Using low-CTE advanced thermal materials, it is possible to tailor CTE, reducing this problem. Sometimes underfill is used to provide mechanical support and protection for the dieto-package interconnects. This can minimize thermal stress on the die due to CTE mismatch with the substrate materials.
As a result of the higher lead free processing temperatures in rework, device packages, initially constructed for lead bearing solders are subjected to greater thermal stresses and exhibit a greater propensity to warp. Some research has demonstrated that the impact of a higher processing temperature, versus the molding temperature, of the package material is a direct causal link to the amount of device warpage. As the device packaging for lead free products have become more stable, this impact has been lessened through material changes in typical BGA packages.
The thinning of area array packages, due to the increasing demand to make end devices more portable, has brought the average moisture sensitivity of device packages up. This makes devices more susceptible to thermal damage based on a given heat exposure time. The purpose of the MSD standard is to identify the moisture sensitivity level at a fixed reflow temperature. The user can then properly store and handle the devices, avoiding subsequent thermal/mechanical damage, during the assembly reflow attachment and/or repair operations. The thinning of the device bodies has moved them to higher MSD levels and shorter floor life, thereby exacerbating the warpage problem.
JEDEC Standard Qualification Levels
Time-to-market pressure for repair depots, as well as leaner inventories, have caused additional turnaround stress on PCB rework departments. Many times, this time pressure on BGA rework means taking short cuts when using hot air rework systems. Matching nozzle size to the BGA is important in minimizing the part warping during rework. Using too small of a nozzle requires all the heat to pass thru the part and into the solder joint. This can cause large temperature differentials and result in BGA warping.
There are several process conditions which need to be controlled in order that warped device packages do not become a problem. The greatest areas to control include: profile development, MSD controls and solder paste volume adjustments made during printing.
Good reflow profile management, in terms of extending the heating/cooling profiles longer, will minimize the impact of device warpage. Although this will impact throughput. During the cool down process, if you go too slowly, it will create coarse-grained structures in the solder joint. Additionally, the proper control of temperature differential, across the part during reflow by using a multizone bottomside heater, will reduce the warpage impact.
To read this entire article, which appeared in the January 2017 issue of SMT Magazine, click here.
Suggested Items
Indium Experts to Present on High-Temperature, Lead-Free Solder Paste and High Reliability Liquid Metal Alloys Poster at ECTC
05/16/2024 | Indium CorporationIndium Corporation Research Associate Kyle Aserian will deliver a presentation at the 74th Electronic Components and Technology Conference (ECTC) on May 31, in Denver, Colorado.
Indium Experts to Present at Electronics in Harsh Environments SMTA Conference
05/13/2024 | Indium Corporationndium Corporation Technical Manager for Europe, Africa, and the Middle East, Karthik Vijay, will deliver a technical presentation and Indium Corporation Senior Technologist, Dr. Ronald Lasky, will deliver both a workshop and technical presentation at the Electronics in Harsh Environments SMTA Conference on May 14-16 in Copenhagen, Denmark.
Connect the Dots: Designing for Reality—The Pre-Manufacturing Process
05/08/2024 | Matt Stevenson -- Column: Connect the DotsI have been working with Nolan Johnson on a podcast series about designing PCBs for the reality of manufacturing. By sharing lessons learned over a long career in the PCB industry, we hope to shorten learning curves and help designers produce better boards with less hassle and rework. Episode 2 deals with the electronic pre-manufacturing process. Moving from CAD (computer-aided design) to CAM (computer-aided manufacturing) is a key step in PCB manufacturing. CAM turns digital designs into instructions that machines can use to actually build the PCB.
AIM Solder Signs Shinil Fl Ltd. as New Distributor for Korea
05/08/2024 | AIM SolderAIM Solder, a leading global manufacturer of solder assembly materials for the electronics industry, is pleased to announce a new distribution partnership with Shinil Fl Ltd., a prominent supplier of technological solutions in the SMT and semiconductor sectors.
Indium Corporation to Showcase HIA Materials at ECTC
05/07/2024 | Indium CorporationAs an industry leader in innovative materials solutions for semiconductor packaging and assembly, Indium Corporation® will feature its advanced products designed to meet the evolving challenges of heterogeneous integration and assembly (HIA) and fine-pitch system-in-package (SiP) applications at the 74th Electronic Components and Technology Conference (ECTC), May 28‒31, in Denver, Colorado.