Deep Into Technology at Compunetics

Estimated reading time: 14 minutes

Schmitt: We had a few customers requesting it at that time. One was a medical customer and this was many years ago. It was an X-ray multi-chip module that had a 35-micron space and trace, that's a 3-mil pitch, and it allowed that X-ray detector to do very high-resolution real-time X-rays. That also included wire-bondable gold ball bonding, etc. That was one of the first big projects we had. One of the second projects we had was for a large government agency, and it was for chip carriers that at the time had 2-mil lines and spaces, and they had microvias. We also installed a nickel heat sink on the board. We made many thousands of these for that customer.

In addition to that, in our early fine line days we did a lot of chip packages with cavities. They had multiple shelves on them. They were all 2-mil lines and spaces, all wire-bondable gold. Another technology that we used at the time was buried resistors. For a supercomputer company on the West Coast, we did BGA cavity boards with buried resistors, and in some cases they were laser-trimmed buried resistors. We also have the capability of doing buried capacitance, which is in use at one of our other divisions.

Some of the other technologies we have are for satellite flight-certified boards. These multilayer flex boards use non-copper conducters. This material is made at our facility. We also have the capability of making heater boards on flex using Inconel conductors and coated with PTFE. This is a standard heater board that is used in the medical industry and in some DOD applications. Also, a NASA X-ray detector on multilayer LCP with 2-mil line/space and ball wire bonding. This was the Rogers product of the year at the International Microwave Symposium seven or eight years ago.

It has been an exciting journey but what’s more important than all this history is the future…what are we working on now and what do we have our eyes set on?

You mentioned padless vias. With the electrophoretic photoresist there is padless via capability. We have interest from a couple of large radar antenna companies and some packaging companies that are interested in padless vias. That's a new technology that we've had, but no one's been interested in it until now, so that may be a technology that will be pertinent and we'll be focusing on in the near future.

Lately we've been doing a lot of work with a new technology called Ormet, which is a process that allows you to bond together sections of printed circuit boards using sintered copper, much like they used to do back in the days of the ‘60s and ‘70s with the first large computers. They're doing that again for antennas, chip testing interposers, etc., with Ormet technology.

We've had our laser drills here for quite a while doing microvias. We do stacked microvias, and we have special chemistry for them in our special reverse pulse plating line. With that and the fine lines, we're able to do flip chip packaging right now down to 200-micron pitch, so we've done quite a few of those for some West Coast customers. Of course, we do lots of flex and rigid-flex. Now we do a few technologies that I'm going to let Jesse talk about, that he's developed for a defense customer. One technology, and there's a lot of interest in this, is used for some of the superconducting chip carriers, interposers, etc., and for quantum computing. I'll let Jesse talk about some of the bumping technologies and three-dimensional boards. 

Jesse Ward: The bump and bonding technology involves copper-plated pillars. They can be down to about 6 mils in diameter, possibly smaller and of variable height, but typically around 2−3 mils in height. What this allows is for an extremely dense mating footprint for essentially testing chips at high speed, usually cryogenic application superconducting. I guess you could think of it as a flip chip alternative. It's occupying a space like a flip chip would but it's not using solder. It's simply pressure contact, so it's reusable. They're getting a lot of uses out of one board, so they can test different chips, the same model, over and over and get a lot of data out of one board before having to discard it and use a new one. The customer really likes the economy they're getting from this. 

We've expanded that to an even more economical solution. At the bump bonding site, you're pressure contacting those bumps so they're reusable, but on the other end of the board you have soldered pins. They've eliminated the soldering of the pins using a castellation. So our customer is using a spring-loaded socket to attach the socket to the PCB. Again, this is non-solderable and it's reusable, so you can kind of think of this board as a 3D board where on the edges of the board are the castellation sites for the spring-loaded socket connector. This can be of any dimension in X and Y. Then it can transpose or connect to blind vias that fan in or out to the chip.

You can essentially think of it as a 3D structure that can have custom dimensions for the chip and custom dimensions for the socket, while having extra areas for mounting the piece. I guess this 3D design was somewhat of a collaboration between Compunetics and another customer, but it was our intellectual property or idea that led to the actual form of the non-standard castellation. It's not a plated through-hole wall—it's different, but we're probably not ready to say what that is yet. The bump bonding is very popular. There are several customers that like it and it seems like it's on the rise.

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