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The closing industry keynote came from Simon Payne, CEO of XJTAG, entitled “Saving Time & Money with JTAG.” He explained that the Joint Test Action Group was originally an electronics industry association initiative for developing a method of verifying designs and testing printed circuit boards after manufacture, and had been subsequently adopted as the IEEE Standard 1149.1-1990 for boundary-scan architecture. JTAG boundary scan technology provided access to many logic signals of a complex integrated circuit, enabling an operating device to be monitored and software and hardware faults to be located. “The good news is it’s already there! You don’t have to pay for it! But are you using it?”
Payne went on to ask, “What is testability?” and commented, “The more testable your design is, the more certain you can be that your test will pick up any defects and your device will work reliably.” He explained the PCOLA-SOQ method for categorising and scoring defects. PCOLA defined the attributes of the component: Presence—is the part there? Correctness—is it the correct part? Orientation—is the part oriented properly? Live—does the part "come alive?" Alignment—is it centred properly on the pad? SOQ defined the attributes of the solder joint: Shorts—are there any shorts? Opens—are there any opens? Quality—is it consistent with the relevant standard?
He discussed the relative strengths, weaknesses and costs of the four test methodologies: JTAG, AOI, X-ray and ICT, in terms of a PCOLA-SOQ analysis. They were appropriate at different stages of the manufacturing process. The benefit of JTAG was that it was available to design engineers. The most important consideration regarding testability was access: a single point of access on a net gave some opportunity for fault detection; multiple points of access gave better detection and the opportunity for fault diagnosis, particularly open circuit location.
Payne reviewed the progress of JTAG over the last decade: costs had fallen and support for non-JTAG devices has become much easier. He stressed that JTAG tools were aimed at board designers as well as production test engineers, and that accelerated in-circuit programming was limited only by flash write speed. Signal integrity in test fixture cabling was becoming an increasingly critical consideration.
He urged designers to think about JTAG as early as possible in the process; the benefits would be realised sooner than might be expected, and time and money could be saved. If JTAG was used to test prototypes, those tests could be re-used on the production line. And accelerated JTAG solutions could be used for in-system programming, both for de-bug and for production.
Lawrence Romine, Altium’s director of Global Business Development, brought proceedings to a close, thanking all who had attended and all who had shared their knowledge and expertise, and the team who had put together such a well-organised and professionally managed event which had exceeded all expectation. The “learn, connect, get inspired” theme was realised with resounding success. Thank you, Altium, for giving me the opportunity to be there.
