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Thermal Management Update with Doug Brooks
January 22, 2018 | Andy Shaughnessy, PCBDesign007Estimated reading time: 1 minute
I had the opportunity to talk with our contributor Doug Brooks recently. He has been doing some research on temperature effects on PCB traces over the last few years, and I wanted to check the status of his latest thermal efforts. He discussed his work with Dr. Johannes Adam, why temperature charts based on a trace in isolation are inaccurate, and how the industry remained so wrong about PCB temperatures for so long.
Andy Shaughnessy: You have done some work on thermal management lately. How did that project start?
Doug Brooks: I wrote an article in the mid-‘90s on trace current/temperature effects, and I used two data sources: the then-current IPC data and some data I found in a 1968 Design News (DN) article. The DN temperatures were about 30% to 40% higher than the IPC temperatures and I wondered why. I began to suspect that it was because of the differences in the way the temperatures were measured or calculated. In looking for a way to confirm that hypothesis, I ran across an article about three years ago written by Dr. Johannes Adam in Germany, and I contacted Johannes.
It turns out that Johannes had written a computer simulation program called TRM (Thermal Risk Management) that was well suited for me to use to look at the data I had used in the article. He offered me a license for the software and we used TRM to simulate the IPC trace data in IPC-2152 and also the earlier data from DN. The simulations were very successful.
Shaughnessy: What did you find out?
Brooks: It turns out the DN data were unreliable!
Shaughnessy: And all of this took place over several years?
Brooks: No. That was just the beginning. It was so easy to simulate the IPC trace data that we began to simulate more realistic scenarios. The IPC data apply to a 6-inch trace in isolation. We began to look at what happens when we change things: change the length, change the pad sizes, add additional adjacent traces, add planes below the trace or on the other side of the board, more common layout conditions like those.
To read this entire article, which appeared in the December 2017 issue of The PCB Design Magazine, click here.
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